Senior IP Verification Engineer — High-speed interface protocols

Job Title

Senior IP Verification Engineer — High-speed interface protocols

Role Summary

Plan, build, and execute verification for AMD Soft IP cores to deliver silicon-proven IP with high quality and zero escapes to production. Work with IP designers, architects, and application engineers across platforms to verify new and existing features and ensure readiness for release.

Experience Level

Senior — typically requires 7+ years of industry experience in IP/SoC design verification.

Responsibilities

Key responsibilities include planning and executing verification strategies, driving closure, and maintaining verification infrastructure.

• Develop verification strategies: test plans, functional coverage models, assertion-based verification, constrained-random tests, and formal verification where applicable.
• Create and maintain comprehensive test plan documentation covering functional coverage, parameter space, platform interactions, and end-user use cases.
• Implement directed and constrained-random tests, parameter configurations, and coverage-closure strategies using UVM/SystemVerilog.
• Drive verification closure using coverage metrics, bug convergence, and quality sign-off criteria.
• Debug complex design and verification issues across digital and firmware interfaces; root-cause failures and collaborate on fixes.
• Review verification architecture, testbench design, and coding standards across the team to promote reuse and standardization.
• Maintain and improve nightly regressions, CI/CD verification flows, and distributed regression infrastructure.
• Promote adoption of best practices: UVM, ABV flows, coverage-driven verification, verification automation, and AI-assisted productivity tools.
• Contribute to IP quality sign-off reviews and pre-release validation across supported platforms and configurations.

Requirements

Must-have skills and experience required to perform the role.

• Proven IP-level ASIC or FPGA functional verification experience and strong RTL debugging skills.
• Hands-on SystemVerilog and UVM testbench development experience.
• Assertion-based verification knowledge (SVA or PSL) and experience with functional and code coverage closure.
• Experience with industry-standard simulators (Questa, Xcelium, VCS, Vivado Simulator) and verification tool flows.
• Experience building and maintaining verification frameworks, regression flows, and CI/CD verification pipelines.
• Scripting for automation: Python, Perl, shell, and build tools (Makefile) experience preferred.
• Experience automating workflows in distributed compute environments (LSF or equivalent).
• Excellent debugging and problem-solving skills; able to debug cross-domain issues involving firmware and platform interactions.

Nice-to-have:

• Formal verification tools and methodologies, simulation acceleration, and coverage-driven verification techniques.
• Exposure to AI-assisted verification tools and verification automation frameworks.
• Prior experience with high-speed interface protocols (HDMI, DisplayPort, MIPI DSI/CSI, USB 3.x/4.0, PCIe Gen4/5, Ethernet, DDR4/DDR5, LPDDR, AXI/AHB/APB) and SerDes/PHY-level verification.
• Leadership or mentorship experience.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.