Senior IP Microarchitect (Sr Lead/Staff)
QualcommJob Title
Senior IP Microarchitect (Sr Lead/Staff)
Role Summary
Technical leader responsible for architecture definition, microarchitecture development, RTL implementation, performance optimization, and silicon delivery for complex custom Infrastructure IPs and interconnect fabrics.
Member of the Custom IP Team working on NoC, PCIe/CXL, memory subsystems, cache coherency, and scale-up interconnects; drives design from concept through production silicon and mentors engineers.
Experience Level
Senior-level. Preferred 8–15 years of experience in SoC/IP architecture, microarchitecture, and RTL design. Minimum-experience options listed in the source: Bachelor's +4 years, Master's +3 years, PhD +2 years.
Responsibilities
Primary responsibilities include defining architectures, delivering RTL, and guiding IP to silicon. Typical tasks:
- Define architecture and detailed microarchitecture for complex custom Infrastructure IPs (datapath, control logic, packet formats, flow control, ordering, coherency, state machines).
- Lead RTL development (Verilog/SystemVerilog) and collaborate with verification, physical design, firmware, and SoC integration teams.
- Evaluate and optimize trade-offs across performance, power, area, scalability, latency, and implementation complexity.
- Design high-performance interconnects, memory subsystem IPs, and protocol-centric solutions.
- Drive design and microarchitecture reviews and make technical decisions across projects.
- Support verification planning, debug, emulation, FPGA validation, and silicon bring-up activities.
- Ensure RTL quality via lint, CDC/RDC checks, synthesis practices, and timing closure methodologies.
- Mentor junior engineers and provide technical leadership within the IP team.
Requirements
Must-have technical skills and experience; education requirements are summarized separately below.
- Extensive experience (preferred 8–15 years) defining and delivering complex custom IP from concept to production silicon.
- Expertise in one or more: Infrastructure IPs, NoC/interconnect fabrics, memory subsystem IPs, cache coherency, or high-speed interface IPs.
- Strong understanding of computer/SoC architecture, digital design methodologies, performance modeling, synchronization, and flow control.
- Hands-on RTL design using Verilog/SystemVerilog and experience with debug and verification flows.
- Familiarity with signoff methodologies: lint, CDC/RDC, synthesis, and timing closure fundamentals.
- Strong analytical, debugging, and communication skills; able to lead technical reviews and cross-team decisions.
- Nice-to-have: experience with emulation/FPGA validation, silicon bring-up, AI infrastructure and scale-up fabric technologies.
Education Requirements
Degree options specified in the source: Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, Electrical/Electronics Engineering, Engineering, or a related field. The posting lists minimum-experience pairings: Bachelor's +4 years, Master's +3 years, or PhD +2 years of relevant hardware engineering experience.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
