Senior HSIO Digital Design Engineer

Job Title

Senior HSIO Digital Design Engineer

Role Summary

Senior digital design engineer on the HSIO (High-Speed I/O) team focused on die-to-die (chiplet) interfaces for AI production platforms. The role works within the San Jose SoC/location group to define architecture, implement digital logic for HSIO PHY/IP, and collaborate with system and analog teams to deliver silicon-ready IP.

Experience Level

Senior-level. Candidates are expected to have industry experience in high-speed digital design; the posting targets engineers with multiple years of relevant experience (see Education Requirements for degree-linked experience guidance).

Responsibilities

Primary technical responsibilities for this role include design, integration, and verification of HSIO digital IP and collaboration across disciplines.

• Design and implement digital logic for HSIO PHY and PHY-adjacent controller IP targeting die-to-die/chiplet interfaces.
• Drive architecture definition and micro-architecture trade-offs for high-speed serial interconnects.
• Collaborate closely with analog/mixed-signal, system, and platform teams to ensure correct digital-on-top flows and silicon integration.
• Perform design-for-test, validation, and verification tasks for HSIO IP; support bring-up and characterization on silicon.
• Work with SI/PI engineers to incorporate signal integrity and power integrity constraints into digital implementation and timing closure.
• Optimize IP for performance, power, and area for AI production platforms and SoC integration.

Requirements

Must-have technical skills and domain knowledge. Degree requirements are summarized separately under Education Requirements.

• Hands-on experience in High-Speed I/O PHY IP development and digital design for high-speed interfaces.
• Strong understanding of high-speed serial interconnect protocols and design trade-offs.
• Solid knowledge of how analog and mixed-signal design and verification affect digital-on-top flows.
• Experience with signal integrity (SI) and power integrity (PI) modeling and applying constraints to digital design.
• Proven ability to collaborate with cross-functional teams (analog, system, verification, platform integration).
• Familiarity with SoC protocols such as AXI, CHI, CXL, PCIe and HSIO PHY layer protocols and architectures is expected.

Education Requirements

BS in Electrical Engineering with ~5+ years of experience, MS in Electrical Engineering with ~3+ years of experience, or PhD in Electrical Engineering. The posting specifically references Electrical Engineering degrees; no certifications were listed. (Degree-and-experience guidance appears in the original posting.)

About the Company

Company: Samsung Semiconductor

Headquarters: San Diego, California, United States

Samsung Semiconductor is a global leader in semiconductor technology, providing innovative solutions for diverse applications including smartphones, electric vehicles, and data centers. As part of Samsung's Advanced Institute of Technology, the company focuses on cutting-edge research in areas such as CPU microarchitecture, AI, and HPC, fostering a diverse and inclusive work environment for its employees to thrive and innovate.