Senior High Speed IO Validation Engineer

Job Title

Senior High Speed IO Validation Engineer

Role Summary

Lead characterization and qualification of high-speed I/O protocols (PCIe, NVLink, UCIe, USB, UFS, Ethernet) across silicon, package, and board for GPUs, CPUs, and SoCs. Work on the Silicon Co-Design team to validate link margin, BER, power per lane, and drive fixes into design, firmware, and manufacturing to ensure production-quality interconnects.

Position is based in Bengaluru, India; hybrid work model.

Experience Level

Senior - typically requires 6+ years of post-silicon HSIO validation, characterization, or closely related experience.

Responsibilities

Primary responsibilities include end-to-end validation, test development, characterization, and cross-functional debug to ensure high-speed IO reliability and performance.

• Lead end-to-end characterization and validation of HSIO (PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet) from die through package and board.
• Develop and execute validation test plans for bring-up, corner qualification, stress, and DOE across PVT, board, cable/connector, thermal, and firmware variables.
• Drive power characterization and optimization under workload-representative stimuli and analyze trade-offs across V/F, lane configuration, and protocol state.
• Perform systematic root-cause analysis for complex HSIO issues, isolating contributions across silicon, package, board, firmware, driver, and system; convert rack-observed failures into silicon/board reproducers.
• Assess manufacturing and yield implications of HSIO margin distributions and feed findings into binning and design decisions.
• Develop and improve validation methodologies, automation frameworks, and margin-tracking infrastructure to increase efficiency and coverage.

Requirements

Must-have technical skills and hands-on lab experience.

Must-have:

• Deep understanding of high-speed serial link protocols and SERDES architecture (equalization, link training, electrical characterization) including PCIe Gen5+/Gen6, NVLink, NVLink-C2C, UCIe, and CXL.
• Strong SI and PI fundamentals: S-parameters, eye diagrams, channel margin, crosstalk, return loss, PDN noise, and jitter decomposition.
• Validation experience across silicon and platform boundaries (CoWoS/interposer/substrate, board), including translating rack-environment effects into silicon/board characterization.
• Hands-on experience with lab instrumentation (DSOs, BERTs, VNAs, protocol/logic analyzers, TDR) and DOE/shmoo/margin-trending.
• Python-based test automation and experience driving cross-functional debug across chip, package, board, firmware, driver, and system teams.

Nice-to-have:

• Experience validating PCIe Gen5/Gen6 or NVLink on production silicon (link training, equalization tuning, BER margining, compliance debug).
• Prior SERDES, mixed-signal, or analog circuit design experience to support Sim-to-Si correlation and propose silicon/system fixes.
• Experience translating rack-environment conditions (thermal, connector reliability, neighbor noise) into silicon/board characterization.
• Familiarity using AI productivity tools for log triage, regression analysis, scripting, and reporting.

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering (or equivalent technical degree). Equivalent practical experience accepted.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.