Senior High-Speed Analog/RF System Architect

Job Title

Senior High-Speed Analog/RF System Architect

Role Summary

Lead the analog/RF and high-speed SerDes architecture for CMOS SoCs that enable graphene photonic interconnects. Define the electrical architecture at the electronics–photonics boundary and translate system-level performance, power, area, and manufacturability targets into scalable SoC solutions while coordinating with photonics, package, analog, digital teams and customers.

Experience Level

Senior-level. Expect multiple years of relevant experience in high-speed analog/RF and SerDes system architecture (typical guidance: senior candidates have several years of domain experience; exact years depend on academic background).

Responsibilities

Own system-level analog/RF and SerDes architecture decisions across the electrical-to-optical channel and deliver product-ready architectures and specifications.

• Own analog/RF and high-speed SerDes architecture for optical transceiver SoCs (drivers, TIAs, equalizers, ADC/DACs, PLLs, CDRs) targeting 112G/224G+ PAM4 and next-generation interconnects.
• Define and maintain Analog Product Requirement Specifications (PRS), verification plans, and PPA (performance, power, area) estimates.
• Drive system-level link budget closure across the complete electrical-to-optical channel, accounting for impairments, channel loss, reflections, crosstalk, and receiver noise.
• Own the Analog IP roadmap and align architecture with technology capabilities, EDA flows, and external design partners.
• Partner with photonics circuit designers, package electrical/SI architects, and SoC teams to reconcile architecture decisions with PIC layout and package constraints.
• Define Customer Requirement Documents (CRDs) and work directly with customers to match architectures to deployment requirements.
• Lead SoC concept and feasibility studies, evaluate architectural trade-offs, and support product teams with modeling and ROI assessment.
• Track and incorporate relevant interconnect standards (PCIe, UCIe, CXL, emerging die-to-die/optical standards) into architecture decisions.

Requirements

Key technical skills and experience required or strongly preferred.

• Proven experience owning high-speed SerDes and analog/mixed-signal system architectures for 56G/112G/224G+ PAM4 in advanced CMOS technologies (FinFET/GAA).
• System-level architecture experience taking heterogeneous SoCs from concept through architecture sign-off; experience with advanced packaging (2.5D/3D integration) is preferred.
• Expertise in electrical–optical link budget analysis and modelling of transmitter/receiver impairments and channel effects.
• Hands-on experience characterizing high-speed analog/RF designs using lab equipment such as BERTs, high-speed oscilloscopes, and VNAs.
• Strong understanding of high-speed interconnect standards (PCIe, UCIe, CXL) and their impact on analog/RF architecture.
• Proficiency with architecture and modeling tools: Cadence Virtuoso/Spectre, MATLAB/Simulink, Keysight ADS, HSPICE, Ansys HFSS/SIwave, and Python-based modeling/automation.
• Excellent cross-domain collaboration and technical communication skills to coordinate with photonics, package, digital teams, product teams, and customers.
• Nice-to-have: experience with silicon photonics or electro-optic interfaces, analog design team leadership, system-level SerDes/optical link modeling, and semiconductor product reliability/qualification.

Education Requirements

Ph.D. in Electrical Engineering or a related discipline with 5+ years relevant experience, or a Master’s degree with 8+ years relevant experience, or equivalent demonstrated impact. Fields: Electrical Engineering, Computer Engineering, Physics, Mathematics, or related technical fields. No specific certifications are required.

About the Company

Company: Black Semiconductor

Headquarters: Aachen, Germany

Black Semiconductor is revolutionizing the semiconductor industry with innovative graphene solutions that enhance chip connectivity and efficiency. By merging electronic computing and photonic communication, the company aims to reshape how chips interact, driving significant advancements in power and speed. Their human-centered approach fosters collaboration and continuous learning, making it a dynamic place for professionals to grow and make an impact.