Senior Hardware Compute Architect

Job Title

Senior Hardware Compute Architect

Role Summary

Own the hardware architecture for a next-generation hybrid compute engine that combines electronic compute and photonic compute technologies. Work with architecture, software, photonics, and implementation teams to produce a system-level architecture that meets performance, power, area, and manufacturability targets.

Experience Level

Senior — typically requires 5+ years designing compute hardware architecture at the SoC or system level.

Responsibilities

Deliver system-level hardware architecture and specifications that enable heterogeneous execution across electronic and photonic domains.

• Define compute architecture: execution units (scalar, vector, tensor/matrix), memory hierarchy, memory tiering, and required interfaces.
• Architect system data fabric and interconnects, addressing bandwidth, latency, coherency, and die-to-die communication requirements.
• Collaborate with software architects to specify HW/SW interfaces and workload mapping strategies.
• Quantitatively evaluate architectural options using performance, power, area, and scalability models to guide pre-silicon decisions.
• Coordinate with photonics, circuit design, RTL, physical design, and packaging teams to translate primitives into implementable designs.
• Own the hardware architecture specification through sign-off and ensure alignment with downstream implementation teams.

Requirements

Minimum technical qualifications and desirable skills.

• Must-have: 5+ years designing compute hardware architecture at the SoC or system level, including heterogeneous compute and accelerators.
• Must-have: Deep expertise in compute architecture: execution units, workload mapping, memory hierarchy, and system-level trade-offs.
• Must-have: Strong experience with high-performance interconnects and data fabrics (UCIe-class, CXL, UALink, NVLink-class or comparable).
• Must-have: Experience with architectural modeling and quantitative analysis of performance, power, area, and scalability; familiarity with performance/power modeling workflows.
• Must-have: Practical experience with architecture modeling and simulation tools and languages (examples: Python, C++, SystemC) and workflows to deliver specs for RTL, physical design, and packaging teams.
• Must-have: Proven ability to collaborate across hardware and software teams and to drive system-level decisions to sign-off.
• Nice-to-have: Familiarity with photonic or optical compute concepts and integration with electronic compute.
• Nice-to-have: Experience with heterogeneous compute platforms (GPUs, DPUs, FPGAs, AI accelerators) or contributing to relevant interconnect standards.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

About the Company

Company: Black Semiconductor

Headquarters: Aachen, Germany

Black Semiconductor is revolutionizing the semiconductor industry with innovative graphene solutions that enhance chip connectivity and efficiency. By merging electronic computing and photonic communication, the company aims to reshape how chips interact, driving significant advancements in power and speed. Their human-centered approach fosters collaboration and continuous learning, making it a dynamic place for professionals to grow and make an impact.