Senior Full-Chip Physical Verification Engineer (Silicon Engineering)

Job Title

Senior Full-Chip Physical Verification Engineer (Silicon Engineering)

Role Summary

Work on full-chip physical verification for advanced-node SoCs that support Starlink silicon. Collaborate with systems, firmware, architecture, design, validation, and ASIC implementation teams to develop and run signoff flows, debug violations, and deliver tapeout-ready designs.

Focus areas include DRC/LVS/PERC/ESD signoff, foundry DRM implementation, flow automation, and coordination of block and top-level signoff activities.

Experience Level

Senior — typically requires 5+ years of ASIC or physical-design flow development experience.

Responsibilities

Primary responsibilities include full-chip verification and signoff:

• Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using Calibre, ICV, or Pegasus.
• Develop, maintain, and optimize physical verification flows for advanced-node SoCs.
• Interpret foundry Design Rule Manuals and translate rule updates into verified flow changes.
• Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs.
• Perform ESD verification and validate protection strategies, current paths, and CDM/HBM compliance.
• Drive tapeout readiness by coordinating signoff across block, top-level, and hard IP teams.
• Engage with foundry teams to resolve DRM ambiguities and waiver requests.
• Develop automation (including AI-assisted tools) for rule-deck validation, violation triage, and signoff reporting.

Requirements

Must-have technical skills and expectations:

• 5+ years of ASIC and/or physical design flow development experience in industry.
• Deep expertise in DRC, LVS, PERC and ESD verification methodologies.
• Hands-on proficiency with Calibre, ICV (IC Validator), or Pegasus.
• Direct foundry DRM experience — able to read, interpret, and implement complex rule decks.
• Experience with advanced nodes (4nm and below) and large SoC designs (>10M gates) and high-frequency designs.
• Strong scripting skills (bash/csh, Perl, Python, Tcl, Makefiles) to automate and maintain flows.
• Ability to work extended hours and weekends as needed to meet critical project milestones.
• Self-driven, proactive, and able to operate in dynamic cross-functional teams.

Preferred: SOC top-level physical design experience (floorplanning, I/O/bump/RDL planning, hard IP integration), IP integration (memories, I/Os, analog IPs, SerDes, DDR), partitioning, and DFT/partition hardening.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science is required.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.