Senior Front End Design Engineer (Microarchitecture)
CerebrasJob Title
Senior Front End Design Engineer (Microarchitecture)
Role Summary
Senior front-end RTL engineer on the Wafer Scale Engine (WSE) team responsible for microarchitecture, RTL design, integration and synthesis to deliver high-performance, power-efficient ASICs. The role works across verification, physical design, software and systems to move architectures from concept to silicon.
This role is based in Sunnyvale and operates in a hybrid work environment.
Experience Level
Senior — typically 8+ years of relevant industry experience (the posting specifies 8+ years).
Responsibilities
Core responsibilities include chip microarchitecture, RTL delivery, and cross-team integration. Key duties:
- Define functional specifications and micro-architecture for front-end blocks.
- Develop, review and maintain high-performance RTL and perform synthesis.
- Integrate third-party IP and front-end chip components.
- Collaborate with physical design to achieve PPA and support design closure.
- Work with design verification and DFT teams to maximize functional and test coverage.
- Coordinate with software and system teams to tune performance and product features.
- Debug silicon-level functional, timing, and power issues during bring-up.
Requirements
Must-have technical skills and experience; nice-to-have items listed separately.
- 8+ years delivering complex, high-performance RTL designs.
- Experience with front-end chip integration and third-party IP integration.
- Proven track record of multiple silicon successes.
- Experience collaborating with external vendors.
- Experience in networking, high-performance computing, machine learning, or related fields.
- Networking stack knowledge: TCP/IP, RDMA, Ethernet.
- Familiarity with PCIe, CPU interfaces, and SerDes technologies.
- Proficient scripting skills (Python, TCL).
- Ability to work in a hybrid environment (onsite in Sunnyvale combined with remote work).
Nice-to-have:
- Experience with FPGA development toolchain: place-and-route, floorplanning, timing analysis.
- Experience managing external ASIC vendors through the product development cycle.
Education Requirements
Master's degree in Computer Science, Electrical Engineering, or equivalent; the posting also allows equivalent practical experience.
About the Company
Company: Cerebras
Headquarters: Sunnyvale, CA, USA
Developer of wafer-scale AI accelerators, Cerebras designs the Wafer Scale Engine (WSE)—one of the world’s largest AI chips—to deliver high-speed training and inference solutions for model labs, enterprises, and AI-native startups.
