Senior FPGA/RTL Design Engineer - Signal Processing
Implement and optimize signal-processing algorithms on FPGAs for Silvus' MIMO wireless networking products. Member of the FPGA Engineering team reporting to the Director of FPGA Engineering; work spans concept, implementation, verification, and field deployment.
Senior β minimum 6 years of FPGA design experience; 4 years with a Master of Science; 2 years with a PhD.
Primary duties include:
Must-have and preferred technical qualifications:
Required: Bachelor of Science in Electrical Engineering, Computer Science, or a related technical field. Preferred: Master of Science in Electrical Engineering (MSEE). PhD referenced as reducing experience requirement. The posting specifies experience-to-degree equivalencies: 6 years without an advanced degree; 4 years with an MS; 2 years with a PhD. No specific certifications were listed.
Company: Silvus Technologies
Headquarters: Irvine, CA, USA
Silvus Technologies is dedicated to connecting those who keep us safe, providing advanced Mobile Ad-hoc Network (MANET) radios powered by custom Mobile-Networked MIMO waveforms. Their technology enables vital communications for mission-critical applications in harsh environments. Following an acquisition by Motorola Solutions, Silvus is expanding its Strategic Growth organization to enhance its impact within U.S. Department of Defense programs.
