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Senior FPGA & Firmware Engineer - SDR

Axon
September 14, 2026
Full-time
Remote friendly (Scottsdale, Arizona, United States)
Worldwide
FPGA Programming Jobs, Level - Senior

Job Title

Senior FPGA & Firmware Engineer - SDR

Role Summary

Deliver FPGA realization of digital signal processing for a software-defined radio used in mesh and connected-device products. Work on algorithm modeling, synthesizable RTL, implementation on Zynq UltraScale+ MPSoC, hardware bring-up, and cross-functional integration with firmware, systems, and RF engineering.

Short mission: build a high-performance OFDM modem and supporting infrastructure to enable reliable wireless communications for public-safety products.

Experience Level

Senior - typically 6+ years of industry FPGA/RTL design experience (architecture through synthesis, timing closure, and hardware bring-up).

Responsibilities

Primary responsibilities include:

  • Research, model, and implement SDR and digital communications algorithms (OFDM, FFT/IFFT, channel estimation/equalization, synchronization, MIMO, FEC).
  • Develop floating- and fixed-point behavioral reference models in MATLAB/Simulink and validate against BER/PER and link-budget requirements.
  • Generate and integrate RTL from Simulink (HDL Coder) and write hand-optimized VHDL/Verilog for performance-critical blocks.
  • Implement designs in Vivado: synthesis, place-and-route, XDC constraints, and timing closure on multi-clock, high-utilization designs.
  • Architect on-chip interfaces and data movement (AXI4/AXI4-Stream, DMA, FIFOs) and design robust CDC logic.
  • Build verification: Simulink/HDL co-simulation, bit-true comparisons, RTL testbenches, and automated regression suites.
  • Integrate modem with RF transceiver front end and ARM application cores; partition functionality across heterogeneous SoC.
  • Bring up and debug hardware using oscilloscopes, logic/protocol analyzers, spectrum/vector signal analyzers, and on‑chip debug (ILA/VIO).
  • Optimize performance, area, and power via micro-architecture refinement, pipelining, and resource sharing.
  • Document design outcomes, produce interface control documents, and present results to the design team; mentor junior engineers.

Requirements

Must-have technical skills and experience:

  • Strong RTL design skills in VHDL and/or Verilog/SystemVerilog with synthesizable coding practices and DFT awareness.
  • Hands-on proficiency with Xilinx/AMD Vivado toolchain: synthesis, implementation, XDC constraints, and timing closure.
  • Experience with MATLAB and Simulink for algorithm modeling and model-based design workflows.
  • Solid foundation in digital signal processing and digital communications (sampling, filtering, FFTs, modulation/demodulation).
  • Experience with fixed-point arithmetic, quantization analysis, and trade-offs between precision, area, and performance.
  • Proficiency with on-chip interconnects and interfaces (AXI4/AXI4-Stream, DMA) and clock-domain-crossing design.
  • Strong RTL verification skills: testbench development, HDL simulation, and verifying RTL against reference models.
  • Practical experience with FPGA/system bring-up and use of lab equipment (oscilloscope, analyzers, ILA/VIO).
  • Effective documentation and presentation skills and ability to work as an independent contributor in cross-functional teams.
  • Familiarity with modern AI-assisted development tools and coding assistants and the ability to apply them judiciously to accelerate design and verification.

Nice-to-have:

  • Experience generating RTL from Simulink (HDL Coder) and optimizing generated code.
  • Hands-on implementation of OFDM modems, channel coding (LDPC, Turbo, Viterbi), synchronization, and MIMO on hardware.
  • Experience with Zynq / Zynq UltraScale+ MPSoC and hardware/software partitioning with embedded processors.
  • Experience integrating wideband RF transceivers (e.g., ADRV9001/ADRV9002) and RF impairment correction such as digital pre-distortion.
  • Familiarity with GNU Radio, Git-based workflows, and CI for HDL/model-based design.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a similar engineering discipline is stated as required. Master’s or PhD in Electrical Engineering, Communications, or Signal Processing is listed as preferred.


About the Company

Company: Axon

Headquarters: Scottsdale, AZ, USA

Axon develops connected devices, software, and cloud services focused on public safety and law enforcement, including body cameras, TASER devices, and digital evidence management to improve safety and accountability.

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Date Posted: 2026-09-14