Senior FPGA Compiler (Router) Engineer

Job Title

Senior FPGA Compiler (Router) Engineer

Role Summary

The Senior FPGA Compiler (Router) Engineer develops and optimizes FPGA routing algorithms within the compiler toolchain to improve performance, routability, and timing closure for next-generation FPGA devices. The role works on compiler-level placement, routing, and timing-driven optimization and collaborates closely with architecture, synthesis, timing, and hardware teams.

Experience Level

Senior — requires 9+ years of experience in FPGA/ASIC design tools, EDA, or related fields.

Responsibilities

Primary responsibilities include:

• Design, implement, and optimize FPGA routing algorithms to improve performance, routability, and timing closure.
• Contribute to compiler flow components, including placement, routing, and timing-driven optimizations.
• Analyze and improve runtime, memory efficiency, and scalability of routing algorithms for large designs.
• Collaborate cross-functionally with architecture, synthesis, timing (STA), and hardware teams to align routing strategies with device capabilities.
• Investigate routing congestion, timing violations, and design bottlenecks; develop solutions to improve convergence.
• Integrate routing features into existing compiler infrastructure and ensure robustness across diverse customer use cases.

Requirements

Must-have technical skills and experience:

• 9+ years experience in FPGA/ASIC design tools, EDA, or related fields.
• Strong algorithms and data structures background, including graph algorithms and optimization techniques.
• Experience with FPGA or ASIC design flows (placement, routing, timing closure).
• Proficiency in C/C++ and software development best practices.
• Familiarity with routing algorithms (e.g., maze routing, negotiated congestion) and timing-driven design methodologies.
• Ability to analyze complex systems and deliver scalable, high-performance solutions.
• Strong communication and teamwork skills for cross-functional collaboration.

Nice-to-have:

• Experience with commercial FPGA toolchains (Quartus, Vivado).
• Knowledge of FPGA architectures and interconnect fabrics.
• Familiarity with parallel/distributed computing for EDA workloads.
• Experience with scripting for tooling and automation (Python, Tcl).
• Background in timing analysis or placement algorithms.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.