Job Title
Senior FPGA/ASIC Verification Engineer
Role Summary
Senior verification engineer responsible for FPGA/ASIC verification, RTL development, and hardware bring-up on complex designs. Works across verification, simulation, synthesis, and implementation flows and provides technical and process guidance to distributed teams.
Experience Level
Senior β typically 5+ years of hands-on FPGA or ASIC development and verification experience.
Responsibilities
Deliver verification and RTL activities across simulation, hardware testing, and implementation lifecycle.
- Develop RTL and verification testbenches using VHDL, Verilog, and SystemVerilog.
- Build and maintain UVM constrained-random verification environments.
- Perform static timing analysis, linting, and clock-domain-crossing (CDC) checks.
- Support requirements capture, architecture definition, synthesis, and placement & routing.
- Coordinate with offshore and site teams; provide technical and process mentorship to junior engineers.
- Perform lab-based FPGA verification and hardware bring-up as needed.
Requirements
Must-have technical skills and hands-on experience.
- Expert-level verification experience with SystemVerilog and/or UVM, or equivalent FPGA hardware verification and lab testing background.
- Substantial hands-on FPGA or ASIC development experience (senior level, ~5+ years).
- Proficiency writing RTL code and testbenches (VHDL, Verilog, SystemVerilog).
- Experience with static timing analysis, linting tools, CDC analysis, synthesis flows, and place-and-route concepts.
- Strong communication skills and demonstrated ability to mentor engineers and coordinate with distributed teams.
- Nice-to-have: experience with Xilinx devices and toolchains.
Education Requirements
Posting specifies a degree in a STEM field (Science, Technology, Engineering, Mathematics). Level of degree not specified.
About the Company
Company: INFT Solutions
Provides engineering staffing and contract services for semiconductor and electronics companies, including design, verification, and test support such as DFT and ATPG expertise.

Date Posted: 2026-08-01