Senior Engineer - Standard Cell Design

Job Title

Senior Engineer - Standard Cell Design

Role Summary

Design and characterize standard cells for new DRAM products and process technologies. Work with DTCO, characterization, and verification teams to produce timing and power models, and develop automation and flows to improve productivity.

The role involves international collaboration and delivery of standard-cell libraries for tapeout and library release, with emphasis on automation and correctness when using AI-assisted tools.

Experience Level

Senior-level. Years of experience not specified.

Responsibilities

Core responsibilities include standard cell design, characterization, modeling, and automation to support DRAM product development.

• Design and maintain standard cells for new DRAM products on new technology nodes.
• Collaborate with DTCO to define standard-cell architecture for emerging technologies.
• Characterize standard cells and produce timing/power models (liberty generation).
• Perform quality analysis of liberty models for performance, power, and functionality.
• Develop automation testbenches, flows, and tools for characterization and data analysis.
• Work with international teams to develop flows and tools for standard-cell design.
• Identify pain points suitable for AI-based automation and collaborate to deploy scalable solutions focused on validation and correctness.

Requirements

Key technical skills and experience.

• Must-have: Strong understanding of CMOS circuit design, device physics, and layout.
• Must-have: Experience across the full standard-cell flow from DTCO/spec definition through library release.
• Must-have: Experience with FinFET and planar technologies.
• Must-have: Experience in standard-cell design, layout, and verification.
• Must-have: Proficiency with characterization and sign-off tools such as Primetime; familiarity with Siliconsmart/Liberate and Solido Analytics preferred.
• Must-have: Familiarity with analog/digital simulation tools (HSPICE, HSIM, Verilog HDL, FINESIM, Simvision).
• Must-have: Scripting and automation skills (Skill, TCL, Perl, Python) for testbench automation and data analysis.
• Preferred: Experience with ICC2 and Synopsys EDA flows; Cadence Virtuoso experience preferred.
• Preferred: Previous work in DRAM memory-related fields or analog blocks.
• Required behavioral: Good interpersonal and communication skills and ability to work effectively in a team.
• Preferred: Experience using AI-assisted tools to improve standard-cell design and characterization productivity, with emphasis on validation and responsible use.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.