Senior Engineer, PLL Design

Job Title

Senior Engineer, PLL Design

Role Summary

Senior analog/mixed-signal engineer responsible for designing high-performance PLL and clocking IP for RF transceivers, SerDes, and high-speed I/O in advanced CMOS processes. Works with digital, layout, and systems teams to deliver IP and support silicon bring-up and characterization.

Experience Level

Senior. The posting indicates a senior/staff level role; no generic overall years-of-experience requirement is stated beyond the education-specific guidance.

Responsibilities

Key responsibilities include architecture, design, verification, and silicon bring-up of PLL and clocking subsystems.

• Design PLLs and clock generation circuits (integer-N, fractional-N, digital PLLs, clock multipliers/dividers) for RF and SerDes applications.
• Design critical PLL building blocks: VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators.
• Perform system-level modeling, noise analysis, and jitter budgeting using MATLAB/Simulink.
• Drive design verification: transistor-level simulation, Monte Carlo analysis, and silicon correlation.
• Collaborate with digital, layout, and systems teams to meet performance, power, and area targets.
• Support bring-up, laboratory characterization, and debug of silicon prototypes.

Requirements

Must-have skills and experience for this role.

• Extensive hands-on PLL design experience in deep-submicron CMOS (5nm–28nm), including one or more topologies such as integer-N, fractional-N, digital PLL, or sub-sampling PLL.
• Deep understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs.
• Proficiency with IC design CAD tools (Spectre, SpectreRF, AMS simulators) and strong MATLAB/Simulink skills for behavioral modeling and system analysis.
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation and RTL implementation of calibration logic.
• Layout-aware design experience and ability to guide critical PLL layout (LC tank, charge pump, reference path).
• Lab characterization experience with phase noise measurement, jitter analysis, and spectrum analysis equipment.
• Experience implementing PLL-related digital calibration circuits (frequency/phase calibration, background self-calibration).
• Strong analytical, problem-solving, and communication skills.

Education Requirements

Master's degree with 2+ years of relevant experience, or PhD with 0+ years of relevant experience, in a related field (as stated in the posting). No specific fields of study or certifications were listed beyond the requirement for a related field.

About the Company

Company: Samsung Semiconductor

Headquarters: San Diego, California, United States

Samsung Semiconductor is a global leader in semiconductor technology, providing innovative solutions for diverse applications including smartphones, electric vehicles, and data centers. As part of Samsung's Advanced Institute of Technology, the company focuses on cutting-edge research in areas such as CPU microarchitecture, AI, and HPC, fostering a diverse and inclusive work environment for its employees to thrive and innovate.