Senior Engineer, Physical Verification Engineering

Job Title

Senior Engineer, Physical Verification Engineering

Role Summary

Responsible for driving full-chip and block-level physical verification (PV) signoff and power-integrity (EM/IR) verification for digital, analog, and mixed-signal ICs. Works with layout, design, CAD/EDA, and foundry teams to ensure signoff readiness and tapeout requirements are met.

Experience Level

Senior engineer / Experienced. The posting indicates an experienced hire; no explicit years-of-experience requirement was stated.

Responsibilities

Execute and lead PV and EM/IR signoff activities, improve flows, and coordinate across teams.

• Plan and own full-chip and block-level PV signoff activities and schedules.
• Run, debug, and resolve violations for DRC, LVS, PEX, PERC/ERC, antenna, density, and DFM checks.
• Perform Electromigration (EM) and IR drop analysis; define power-integrity strategies for blocks and full-chip designs.
• Analyze static and dynamic IR drop issues, correlate simulations with design requirements, and recommend fixes.
• Review and implement foundry rule deck updates; maintain signoff rule sets.
• Collaborate with layout, circuit, package, and PD teams to optimize power delivery and achieve signoff.
• Develop and maintain automation, scripts, dashboards, and reporting to improve PV and EM/IR productivity (Python, Tcl, Shell, SKILL).
• Support tapeout readiness reviews, produce signoff documentation, and close reliability signoff items before tapeout.
• Participate in design and signoff reviews; mentor junior engineers and provide technical guidance.

Requirements

Must-have technical skills and experience to perform PV and EM/IR signoff for mixed-signal ICs.

• Proven experience leading PV signoff (DRC, LVS, PEX, PERC/ERC, antenna, DFM) on full-chip and block levels.
• Hands-on experience with EM and IR analysis and power-integrity verification for digital, analog, and mixed-signal designs.
• Proficiency scripting in Python, Tcl, Shell, or SKILL to automate flows and reporting.
• Experience working with foundry rule decks and implementing rule updates.
• Ability to debug complex PV and EM/IR violations and recommend design or grid changes for signoff.
• Strong collaboration skills with physical design, layout, circuit, CAD/EDA, and foundry support teams.
• Experience producing signoff documentation and participating in tapeout planning.
• Willingness to travel as required (the role lists ~10% travel).

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.