Senior Engineer, Physical Verification Engineering

Job Title

Senior Engineer, Physical Verification Engineering

Role Summary

Senior engineer responsible for full‑chip and block‑level physical verification (PV) and power‑integrity signoff for digital, analog, and mixed‑signal ASIC designs. Works within the India PDC PV team and collaborates with layout, circuit, PD, CAD/EDA, and foundry teams to ensure timely signoff and tapeout readiness.

Drive PV and EM/IR methodology, automation, and reporting to improve productivity, turnaround time, and reliability.

Experience Level

Senior-level (experienced). The posting indicates an experienced/higher-level engineering role; no specific years of experience were listed.

Responsibilities

Primary responsibilities focus on physical verification signoff, EM/IR analysis, cross-team collaboration, and automation.

• Own and drive full‑chip and block‑level PV signoff activities.
• Perform and debug DRC, LVS, parasitic extraction (PEX), PERC/ERC, antenna, density, and DFM checks.
• Analyze and resolve complex PV violations while maintaining schedule commitments.
• Review and implement foundry rule deck updates and work with layout and design teams to achieve clean signoff.
• Support tapeout readiness reviews and prepare signoff documentation.
• Perform Electromigration (EM) and IR drop analysis; define power integrity verification strategies for blocks and full‑chip designs.
• Analyze static and dynamic IR drop issues, debug EM violations, and recommend corrective actions to optimize power grids.
• Correlate simulation results with design requirements and reliability specifications; track and close reliability signoff requirements before tapeout.
• Develop methodologies, automation, scripts, dashboards, and reporting mechanisms for PV and EM/IR flows.
• Participate in design reviews, signoff reviews, and tapeout planning meetings; mentor junior engineers and provide technical guidance.

Requirements

Must-have technical skills, tool experience, and collaborative behaviors.

• Proven experience with PV flows: DRC, LVS, PEX, PERC/ERC, antenna, density, and DFM checks.
• Practical experience with EM/IR analysis and power‑integrity verification for digital, analog, and mixed‑signal designs.
• Hands-on scripting and automation experience using Python, Tcl, Shell, or SKILL to develop PV and EM/IR flows and utilities.
• Ability to debug complex violations, optimize power grid structures, and correlate simulation results to requirements.
• Experience interacting with layout, circuit, PD, CAD/EDA, and foundry support teams and driving signoff to tapeout.
• Strong communication skills and experience mentoring junior engineers.
• Willingness to travel as required (approximately 10%).
• Export-control consideration: non‑US applicants may require export licensing approval to access certain technical data.

Education Requirements

Not specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.