Senior Engineer, Physical Design - Interconnects
SiFiveJob Title
Senior Engineer, Physical Design - Interconnects
Role Summary
As a Senior Physical Design Engineer (Interconnects), you will deliver RTL-to-GDSII physical implementation for high-speed SoC interconnects including Network-on-Chips (NoC), coherent CPU clusters, and uncore subsystems. You will work with architecture and system teams to meet aggressive power, performance, and area (PPA) targets on advanced FinFET process nodes.
Work on core RISC-V infrastructure used across SiFive products.
Experience Level
Senior — typically 4+ years of hands-on physical design experience, especially on FinFET nodes (7nm or below).
Responsibilities
Accountable for end-to-end physical implementation and collaboration with architecture and system teams.
- Lead RTL-to-GDSII implementation for complex system IP: NoC fabrics, coherent clusters, and memory subsystem logic.
- Partner with architects to perform IP-physical co-design, identify physical bottlenecks, and propose microarchitectural or pipelining changes.
- Develop and refine system-level floorplans for large, bus-heavy subsystems.
- Resolve system-level physical challenges such as timing closure on wide/high-frequency buses and global clock distribution.
- Implement and improve automated flows for synthesis, place-and-route, and sign-off; contribute to internal scripts and methodology.
Requirements
Minimum qualifications and core skills required for this role.
- 4+ years of hands-on physical design experience focused on closing high-performance blocks in FinFET nodes (7nm or below).
- Strong understanding of SoC building blocks: NoC architectures, coherent interconnects, and cache-coherent clusters; able to read RTL to infer design intent.
- Mastery of hierarchical implementation techniques, including partitioning, timing budgeting, and multi-mode multi-corner (MMMC) timing closure.
- Proficiency with Synopsys and/or Cadence implementation and sign-off toolflows.
- Data-driven approach to optimizing PPA and clear communication skills for cross-functional collaboration.
Nice-to-have:
- Experience with large-system floorplanning and automation/scripting to streamline implementation flows.
Education Requirements
BS or MS in Electrical Engineering, Computer Engineering, or a related technical field.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
