Senior Engineer, Physical Design Engineering (ASIC)

Job Title

Senior Engineer, Physical Design Engineering (ASIC)

Role Summary

The Senior Physical Design Engineer will lead implementation and delivery of complex digital and mixed-signal IC designs across the backend flow, from floorplanning through place-and-route, timing closure, physical verification, and tapeout support.

This role works cross-functionally with RTL, STA, DFT, verification, IP/library, and package teams to turn RTL and architecture intent into manufacturable silicon while improving methodology and automation.

Experience Level

Senior-level. The posting references equivalent combinations of education and typically 5+ years of related experience; the title indicates a senior engineering role responsible for independently driving complex blocks and mentoring junior engineers.

Responsibilities

Primary responsibilities include leading physical implementation, ensuring signoff readiness, and improving flows and automation.

• Own physical design implementation for complex blocks and subsystems: floorplanning, placement, CTS, routing, and physical optimization.
• Drive timing closure, congestion analysis, power optimization, and area improvements.
• Perform physical verification activities (DRC, LVS, ERC, reliability checks) in coordination with verification teams.
• Develop and maintain physical design constraints, scripts, and flow improvements to increase quality and efficiency.
• Collaborate with RTL, STA, DFT, design verification, library, and package engineering to resolve implementation issues.
• Support block-level and top-level integration, interface planning, and implementation readiness.
• Analyze and debug timing, signal integrity, power, and other backend implementation issues.
• Contribute to methodology and automation improvements and participate in design reviews.
• Author and maintain implementation documentation, constraints, and signoff status.
• Mentor junior engineers and provide technical leadership on execution and debugging.
• Support tapeout planning and execution to meet project milestones.
• Willingness to travel up to 10% as required.

Requirements

Must-have technical skills and experience to perform the role; preferred items are listed separately.

• Proven experience in physical design for ASIC/SoC development through successful tapeouts.
• Expertise in floorplanning, place-and-route, clock tree synthesis, timing closure, and physical verification signoff.
• Strong understanding of timing analysis, constraints, signal integrity, and power optimization.
• Experience with industry-standard physical design and signoff tools, including Cadence-based flows.
• Scripting experience (TCL, Python, or similar) for automation and flow improvement.
• Demonstrated problem-solving and debug skills across backend implementation challenges.
• Experience collaborating with RTL, STA, DFT, design verification, and package/product engineering teams.
• Clear technical communication and documentation skills; ability to independently drive major implementation workstreams.

• Nice to have: advanced-node implementation, low-power design methodologies, mixed-signal integration experience, backend flow or automation improvement experience, prior mentoring or technical leadership.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field is listed as preferred. The posting also allows an equivalent combination of education and related experience (examples cite 5+ years of related experience in lieu of a degree).

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.