Senior Engineer, Physical Design and Signoff (Synthesis to GDS2)

Job Title

Senior Engineer, Physical Design and Signoff (Synthesis to GDS2)

Role Summary

Work on RTL-to-GDS implementation and signoff for on-chip SLM monitors and silicon biometrics using modern ASIC digital flows. The role covers synthesis, pre- and post-layout STA, physical verification, and timing/power signoff across IP/block/full-chip levels on advanced process nodes.

Collaborate with architects, circuit designers, and cross-functional teams to develop flows, perform tape-outs, and deliver robust timing and reliability closure.

Experience Level

Senior. The posting requests candidates with industry experience; the listed guideline is 3+ years of relevant experience.

Responsibilities

Deliver physical design and signoff tasks across the RTL-to-GDS flow and support tape-out activities.

• Conceptualize and productize RTL-to-GDS flows for SLM monitors and related IP.
• Design on-chip monitors for process, voltage, temperature, glitch detection, and droop monitoring.
• Perform synthesis, pre-layout STA, develop SDC constraints, and support floorplanning and placement.
• Execute power planning, bump placement, CTS, routing, and MV design techniques (UPF-aware flows).
• Drive post-layout STA, timing ECOs, timing signoff methodology, and closure for high-frequency IP.
• Perform physical verification tasks including DRC, LVS, PERC, ERC, antenna checks, EMIR, and power signoff.
• Collaborate with architects and circuit teams to create and refine flows and methodologies.
• Characterize timing models and ensure reliability and aging corners are met for automotive and consumer products.

Requirements

Must-have technical skills and experience; education details are summarized separately below.

• Strong hands-on experience in Physical Design, Physical Verification, and pre-/post-layout STA, including timing closure.
• Experience with EMIR and power signoff; SDC development and UPF/multivoltage design flows.
• Mandatory experience with DRC, LVS, DFM cleaning, and timing closure.
• Proficiency with digital EDA tools (vendor-agnostic); familiarity with Synopsys toolchain is preferred (e.g., Fusion Compiler, VCLP, IC Compiler, PrimeTime, PrimeTime-PX, ICV, RedHawk).
• Experience with advanced process nodes (14nm → 2nm) and successful tape-outs.
• Good understanding of OCV/POCV, derates, crosstalk, design margins, and reliability considerations.
• Scripting experience for flow automation and methodology development (TCL, Perl).
• Ability to work independently and communicate effectively with global teams.

Education Requirements

Bachelor's (B.S./B.Tech) or Master’s (M.S./M.Tech) in Electrical Engineering is specified. The posting requests 3+ years of relevant industry experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.