Senior Engineer, Low Power Verification & Formal Equivalence
SiFiveJob Title
Senior Engineer, Low Power Verification & Formal Equivalence
Role Summary
Lead execution of low-power static checks and formal logical equivalence signoff for advanced RTL-to-GDSII flows. Work with architecture, physical design, and power teams to implement, verify, and debug UPF and equivalence flows including late-stage ECOs.
This role is based in Bengaluru; employment is contingent on the right to work in India and satisfactory background checks and export-control clearance where required.
Experience Level
Senior level. The role expects 3+ years of relevant industry experience in ASIC/SoC design and verification.
Responsibilities
Primary responsibilities include ownership of low-power signoff and formal equivalence for assigned blocks and collaboration with backend teams.
- Own static low-power verification signoff across assigned design blocks to prevent structural low-power bugs.
- Develop, deploy, and maintain UPF coding and verification flows; automate UPF tasks and align with platform methodology.
- Own Logical Equivalence Checking (LEC) and formal equivalence flows from RTL through post-route netlists, including formal ECOs.
- Debug power-intent and physical-design related violations; propose implementable UPF and equivalence solutions with PD and power teams.
- Execute late-stage ECOs and ensure equivalence and power intent integrity after implementation changes.
Requirements
Must-have technical skills and proven experience for immediate contribution.
- 3+ years of industry experience in ASIC/SoC design and verification.
- Practical experience coding, debugging, and maintaining Unified Power Format (UPF) power intent.
- Experience running, analyzing, and debugging static low-power checks on RTL and post-PNR netlists using industry tools (example: Synopsys VC Low Power / VCLP).
- Hands-on experience with Logical Equivalence Checking (LEC) and formal equivalence tools (example: Synopsys Formality) and implementing formal ECO flows.
- Technical understanding of power-management library cells and implications of Isolation (ISO), Level Shifters, Always-On (AON) cells, and retention registers.
- Nice-to-have: foundational backend Physical Design knowledge and scripting/automation skills (Tcl, Python, or Perl) to improve flows and parse logs.
Education Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting specifies a Bachelor's plus 3+ years of industry experience in ASIC/SoC design and verification.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
