Senior Engineer - Low Power CLP
ArmJob Title
Senior Engineer - Low Power CLP
Role Summary
Work in Arm's Solutions Engineering group to validate RTL-to-gate and gate-to-GDS implementations, ensure power intent correctness, and enable signoff-quality silicon. The role focuses on low-power structural verification, logic equivalence checking, and automation to support complex SoC and IP designs.
Experience Level
Senior level — typically 5+ years of relevant experience in logical signoff and low-power verification for SoC/IP development.
Responsibilities
Contribute to signoff flows and debug closure across RTL, netlist, and physical stages; develop automation and methodology improvements.
- Perform low-power structural verification using Cadence Conformal Low Power (CLP) or Synopsys VCLP.
- Verify and validate UPF implementation across RTL, netlist, and physical design stages.
- Perform power-aware equivalence checking and resolve non-equivalences and aborts.
- Analyze, debug, and resolve CLP/VCLP structural, rule-based, and power-aware verification failures.
- Execute RTL-to-synthesis, synthesis-to-P&R, and ECO logic equivalence verification using Conformal LEC or equivalent tools.
- Develop, automate, and maintain LEC and low-power verification flows; produce signoff reports.
- Build reusable debug utilities and scripts to improve verification productivity and scalability.
- Collaborate with design, verification, and implementation teams to drive verification closure.
Requirements
Key qualifications and technical skills required for successful performance in this role.
- Must-have: 5+ years of experience in logical signoff and low-power structural verification for SoC/IP projects.
- Must-have: Hands-on experience with low-power verification tools (Cadence Conformal Low Power or Synopsys VCLP) and power-aware LEC.
- Must-have: Strong knowledge of UPF/CPF and SystemVerilog; ability to analyze and resolve verification failures.
- Must-have: Experience developing automation (TCL, Perl, Python) and maintaining verification flows.
- Nice-to-have: Understanding of synthesis and Place & Route (P&R) flows and SoC-level flat LEC runs.
- Nice-to-have: Prior experience driving signoff methodologies and generating comprehensive signoff reports.
Education Requirements
Not specified.
About the Company
Company: Arm
Headquarters: Cambridge, United Kingdom
ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.
