Senior Engineer II - Physical Design
MicrochipJob Title
Senior Engineer II - Physical Design
Role Summary
Member of the AES Physical Design team responsible for implementing RTL-to-GDSII for large SoCs. Work includes floor-planning, place & route, timing closure, physical verification, IP integration and first-pass silicon delivery.
The role partners with implementation and project teams to resolve physical design issues across multiple blocks and top-level designs at advanced nodes (40nm to 3nm and below).
Experience Level
Senior - requires 7+ years of physical design experience.
Responsibilities
Accountable for physical implementation and verification of complex blocks and subsystems; ownership from floorplan through sign-off and handoff for tapeout.
- Floor-planning, placement, routing and clock tree synthesis (CTS) for multiple blocks and full-chip.
- Timing closure, static timing analysis and crosstalk analysis.
- Power integrity: IR/EM analysis and signoff.
- Physical verification (DRC/LVS) and IP integration (analog IP, hard/soft macros).
- Develop and maintain physical design flow and methodology for hierarchical designs.
- Lead and mentor junior engineers and coordinate with RTL, synthesis, DFT and verification teams.
- Use metric-driven techniques to improve first-pass silicon success; report status and resolve issues with project leads.
- Occasional travel as required (0–25%).
Requirements
Must-have technical skills, tools experience and professional competencies.
- 7+ years of hands-on physical design experience at advanced process nodes (40nm to 3nm and below).
- Proven expertise in floor-planning, P&R, CTS, extraction, and physical verification (DRC/LVS).
- Strong knowledge of place-and-route and low-power methodologies; timing closure expertise.
- Familiarity with synthesis and DFT concepts and flows.
- Experience with backend EDA tools such as Innovus or ICC2; signoff tools like Calibre/PVS, PrimeTime/Tempus, Redhawk/Voltus, and QRC/Starrcxt.
- Proficient scripting/programming skills (Perl, TCL, Shell and/or Python) for automation and flow development.
- Experience integrating analog IP, hard/soft macros, and delivering hierarchical chip designs.
- Excellent written and verbal communication skills; ability to work with global teams and lead junior staff.
Education Requirements
Requires a B.E./B.Tech. or M.Tech. in Electronics.
About the Company
Company: Microchip
Headquarters: Chandler, Arizona, USA
Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.
