Senior Engineer II - CAD (Physical Verification)

Job Title

Senior Engineer II - CAD (Physical Verification)

Role Summary

Join Microchip's CAD group to develop and support back-end physical verification flows and tools for multiple technology nodes. You will build and maintain verification run decks, automate flows, debug verification issues, and support layout and design engineers worldwide.

Work spans digital and analog design styles and requires coordination with technology development and device engineering to ensure manufacturable, reliable designs.

Experience Level

Senior-level. Typical candidates have 7+ years of relevant physical-verification experience; the team assigns tasks based on individual experience and expertise.

Responsibilities

Primary duties include development, support, and automation of physical verification flows and tools.

• Develop regression test cases and QA suites for physical verification decks and PDKs.
• Support layout and design engineers with DRC/LVS/PERC using Calibre, Pegasus, or equivalent tools.
• Develop and maintain verification run decks, rule decks, and PERC setups.
• Debug verification failures using visualizers (RVE, Vue) and adjust flows accordingly.
• Work with Technology Development and Device Engineering to implement DRC rules and DFM checks.
• Verify and enhance foundry rule decks across multiple process nodes and foundries.
• Support remote sites worldwide and respond to PV issues and escalations.
• Contribute to flow improvements that increase device quality, reliability, and yield.

Requirements

Must-have technical skills and experience for effective performance in this role.

• Expertise with Siemens Calibre and/or Cadence Pegasus for DRC, LVS and PERC; strong experience developing and running verification decks.
• In-depth knowledge of Calibre DesignRev scripting; fluent in SVRF and TVF.
• Experienced debugging PV issues using RVE, Vue, or similar EDA visualizers.
• Proficient scripting and automation skills (Tcl/Tk, Perl, Python) both inside and outside EDA tools.
• Strong understanding of layout rules, device identification, and foundry rule semantics.
• Knowledge of DFM solutions impacting quality, reliability, and yield.
• Familiarity with Cadence Virtuoso and/or CalibreDRV.
• Excellent verbal and written communication and teamwork skills.
• Nice-to-have: experience with extraction, reliability, dynamic noise, and multiple foundry PDKs (4nm to larger nodes).

Education Requirements

Bachelor's degree with 7–8 years of experience in physical verification or a related area, or a Master's degree with 5–6 years of experience. Field of study not specified.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.