Senior Engineer II - Backend Implementation

Job Title

Senior Engineer II - Backend Implementation

Role Summary

Member of the AES Design implementation team responsible for static timing analysis (STA) and timing closure for large SoC blocks and top level. Work focuses on SDC/constraints generation, pre- and post-layout timing, and low-power checks across advanced process nodes.

Collaborate with implementation, verification and project teams; mentor junior engineers and drive implementation milestones.

Experience Level

Senior - requires 7+ years of STA/implementation experience on complex SoC designs.

Responsibilities

Key responsibilities include timing closure, constraints development, verification, and design optimization across blocks and full chips.

• Perform STA timing closure for multi-million-gate hierarchical designs.
• Develop and maintain timing constraints (SDC) and timing models; perform pre- and post-layout timing analysis.
• Run CLP and LEC for both block-level and full-chip verification.
• Insert and validate DFT logic at block and top level.
• Analyze timing and crosstalk issues; provide placement and CTS guidance.
• Optimize design performance through timing and power closure techniques.
• Lead and drive team members to complete implementation activities.
• Use metric-driven techniques to improve first-pass silicon success.
• Communicate status and technical issues to project management and cross-functional teams.
• Occasional travel (0–25%).

Requirements

Must-have technical skills and experience; items noted as "nice-to-have" are preferred but not required.

• 7+ years of STA/implementation experience on advanced-node SoC projects.
• Proven expertise in static timing analysis, timing closure and crosstalk analysis.
• Experience with synthesis and STA tools such as Genus, Fusion Compiler, and Primetime or Tempus.
• Strong scripting skills in Perl, TCL, Shell, and/or Python.
• Solid understanding of Verilog and digital design flows.
• Understanding of DFT insertion and related flows.
• Excellent written and verbal communication skills for global collaboration.
• Nice-to-have: Conformal LEC and CLP experience, UPF/CPF low-power flows, and prior work on advanced nodes (16nm–3nm).

Education Requirements

Requires at least a B.E. / B.Tech. / M.Tech. in Electronics as stated in the posting.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.