Senior Engineer - HBM Design for Test (DFT)

Job Title

Senior Engineer - HBM Design for Test (DFT)

Role Summary

The Senior Engineer is an experienced technical contributor responsible for defining, implementing, integrating, and supporting Design-for-Test (DFT) solutions across HBM core and base die for current and next-generation HBM products.

This role drives DFT architecture and specifications, partners with design, test, verification, and product teams, and supports tape-out, silicon bring-up, and product qualification.

Experience Level

Senior — typically 5+ years of semiconductor development experience, with specific exposure to DFT, design, verification, test, or silicon debug.

Responsibilities

Key responsibilities include designing and integrating DFT features for HBM, coordinating across engineering functions, and supporting silicon validation and manufacturability.

• Define, implement, and integrate DFT features for assigned HBM core and base die designs in line with DFT architecture and guidelines.
• Develop, review, and maintain DFT specifications, requirements, and implementation guidelines.
• Ensure DFT implementations meet test, quality, and manufacturability requirements for HBM products.
• Collaborate with Design Engineering, Product Engineering, Test, and DFT Verification to translate manufacturing/test requirements into DFT implementations and align verification coverage.
• Identify, debug, and resolve DFT-related issues during build execution, tape-out, and silicon bring-up.
• Serve as a DFT contributor or sub-domain owner for assigned programs; support reuse and standardization of DFT logic and methodologies.
• Participate in design, verification, and readiness reviews and document implementations and lessons learned.
• Leverage AI tools where appropriate to improve DFT workflows and job functions.

Requirements

Must-have technical experience and skills for successful performance in this role.

• 5+ years of semiconductor development experience with exposure to DFT, design, verification, test, or silicon debug.
• Experience with memory architectures; HBM or DRAM experience preferred (1+ years noted in source).
• Experience implementing DFT features and supporting DFT-related debug and bring-up activities.
• Experience working with DFT verification teams and coverage methodologies (preferred).
• Familiarity with manufacturing test flows and test requirements for advanced memory products (preferred).
• Strong written and verbal communication skills and ability to work in a multi-functional, program-driven environment.

Education Requirements

Bachelor's degree in Electrical Engineering or a related field is required; Master’s degree preferred. (Source specifies Bachelor's required and Master’s preferred.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.