Senior Engineer, Design Verification

Job Title

Senior Engineer, Design Verification

Role Summary

Member of Marvell's CXL Product Development team responsible for functional verification of complex SoCs for composable datacenter products. The role focuses on verification planning, developing verification environments, simulation and debug, and collaborating with design and validation teams to reach sign-off.

Experience Level

Senior-level. Typical background: BS in Electrical/Computer Engineering plus ~2 years relevant experience, or an MS in Electrical/Computer Engineering.

Responsibilities

Primary responsibilities include planning and executing verification for complex designs and improving verification methodology.

• Create and execute verification plans for complex SoCs (RTL and gate-level).
• Develop constrained-random verification environments, testbenches, checkers, monitors and drivers using Verilog/SystemVerilog and UVM.
• Use Synopsys VCS for simulation and Synopsys Verdi for debug and waveform analysis.
• Write and maintain verification scripts and utilities in C/C++ and Python.
• Debug failing simulations, generate test vectors and scenarios to exercise designs exhaustively.
• Drive and analyze coverage metrics and develop coverage models and test plans.
• Collaborate with design engineers and post-silicon validation teams to resolve issues and close verification tasks.

Requirements

Must-have technical skills and experience. Degree information is summarized separately below.

• Experience with Synopsys VCS (simulation) and Synopsys Verdi (debug).
• Proficient in Verilog, SystemVerilog and UVM-based verification.
• Strong scripting and programming skills in C/C++ and Python.
• RTL design debug and functional verification techniques, including assertion-based and constrained-random verification.
• Familiarity with AMBA AXI4 protocol and PCIe fundamentals.
• Experience developing test plans, coverage models, and using coverage metrics to guide verification closure.
• Knowledge of advanced computer architecture concepts relevant to SoC verification.
• Nice-to-have: gate-level verification and post-silicon validation experience.

Education Requirements

BS in Electrical or Computer Engineering with ~2 years of relevant experience, or an MS in Electrical or Computer Engineering. The posting also expects applicants to have relevant work/internship experience or completed graduate coursework/research covering the listed verification technologies and methodologies.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.