Senior Engineer - DEG Layout

Job Title

Senior Engineer - DEG Layout

Role Summary

Design and deliver high-quality physical layouts for analog, mixed-signal and custom digital blocks, standard cells and full-chip integrations in advanced CMOS processes. Work with global engineering teams to meet tape-out schedules and ensure layouts meet electrical and manufacturing constraints.

Experience Level

Senior — typically 5 to 8 years of relevant analog/custom layout experience.

Responsibilities

Primary responsibilities focus on layout implementation, verification and project delivery for critical analog and mixed-signal IP.

• Create block- and chip-level layouts for analog, mixed-signal and custom digital blocks, and standard cells.
• Perform physical verification including DRC, LVS, antenna, matching, latch-up, EM/IR and other process checks; document results.
• Develop digital block layouts using auto place-and-route tools where applicable.
• Implement automation and basic skill coding to reduce manual effort and improve throughput.
• Estimate area/time, plan and execute layout schedules across multiple concurrent projects.
• Review and mentor junior layout engineers; provide guidance on sub-block layouts and quality expectations.
• Coordinate with global engineering teams to resolve layout-related issues and support successful tape-outs.
• Explore and apply AI/automation tools to improve layout efficiency.

Requirements

Essential technical skills and experience required for successful performance in this role.

Must-have

• 5–8 years of analog/custom layout experience in advanced CMOS processes.
• Hands-on experience creating layouts for critical analog blocks (examples: temperature sensor, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pump, current mirrors, comparators, differential amplifiers).
• Expertise with Cadence layout tools (VLE/VXL) and Mentor Graphics Calibre for DRC/LVS.
• Strong understanding of analog layout fundamentals (matching, electro-migration, latch-up, coupling/crosstalk, IR-drop, parasitics) and how layout affects speed, capacitance, power and area.
• Proven skills in physical verification and problem solving for custom layouts.
• Effective verbal and written communication skills to work with cross-functional teams.

Nice-to-have

• Experience supporting multiple tape-outs and full-chip integrations.
• Experience with automation, scripting and use of AI tools to reduce layout effort.
• Experience with digital auto placement and routing flows for mixed-signal designs.
• Leadership experience in planning, delegation and execution across projects.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.