Senior Engineer, DDEG Design Methodology

Job Title

Senior Engineer, DDEG Design Methodology

Role Summary

Lead verification and analysis for full-chip and block-level DRAM and emerging memory designs, with focus on gate-level, low-power, and power-management technologies. Collaborate with global design and verification teams to develop verification methodology, testbenches, automation, and debug flows that improve coverage and accelerate time to silicon.

Use automation and AI-based tools responsibly to shorten verification cycles and improve debug efficiency while validating outputs against specifications and simulation evidence.

Experience Level

Senior — typically 7+ years of relevant experience in memory design verification, complex CMOS or gate-level circuit analysis, and verification methodology.

Responsibilities

Primary duties and scope of work.

• Adopt AI-based tools, agentic workflows, and automation frameworks to speed verification, assist test-case/testbench development, and improve debug across simulation and silicon learning loops.
• Validate AI outputs before adoption: review assumptions, align with specs/standards, cross-check with simulations, waveforms, assertions and coverage reports, and document accepted/changed results.
• Provide verification support by simulating, analyzing, and debugging pre-silicon block and full-chip designs; develop testcases and stimulus to increase functional coverage for DRAM and emerging memory architectures.
• Develop and maintain testbenches and test vectors; run regressions and perform coverage analysis and improvements.
• Co-develop new verification flows and methodologies with international colleagues to address challenges in advanced DRAM and emerging memory designs.
• Guide and mentor new and energetic engineers on the team.

Requirements

Must-have technical skills and experience. Nice-to-have items noted when applicable.

• SystemVerilog and UVM testbench development experience; PLI coding experience.
• Proficient with Verilog and SPICE simulations or equivalent simulation environments.
• Experience in DRAM, SRAM, or related memory domains (preferred).
• AMS verification and co-simulation experience.
• Familiarity with simulation and debug tools such as Virtuoso, Xcelium, Simvision, vsim, Waveview, Finseim, and Hspice.
• Scripting and automation skills (Perl, Python) to build flows and regressions.
• Hands-on experience building SV testbenches at block and full-chip level; strong SV/UVM-based verification background.
• Strong analytical and debugging skills, and effective communication and teamwork abilities.

Education Requirements

Bachelor's or postgraduate degree in Electronics Engineering or a related engineering field required.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.