Senior Engineer, DDEG Design Methodology

Job Title

Senior Engineer, DDEG Design Methodology

Role Summary

Responsible for verification, simulation, and debug of pre-silicon block-level and full-chip gate-level custom DRAM designs with advanced low-power and power-management features (DDR4/LPDDR4/DDR5/LPDDR5). Works with global design and verification teams to own verification flows and improve verification efficiency through automation and AI-assisted tooling.

Experience Level

Senior level. No explicit years-of-experience stated.

Responsibilities

Provide verification and analysis support across block and full-chip designs; improve verification productivity through tooling, automation, and disciplined validation of results.

• Leverage AI-based tools, agentic workflows, and automation frameworks to accelerate verification cycles, assist in test-case and testbench generation, and improve debug efficiency across simulation and silicon loops.
• Validate AI outputs and automation results against specifications, simulations, waveforms, assertions, and coverage reports; document accepted changes.
• Simulate, analyze, and debug pre-silicon block and full-chip designs; develop test cases and stimulus to increase functional coverage for DRAM and emerging memory architectures.
• Develop and maintain testbenches and test vectors; run regressions and perform coverage analysis and improvement.
• Collaborate with international colleagues to develop new verification flows and verification methodology for advanced memory products.
• Participate in cross-functional design and verification reviews and support debugging through simulation and waveform analysis.

Requirements

Must-have technical skills and team abilities; nice-to-have items listed separately.

• Proven experience with SystemVerilog and UVM-based verification; ability to build SV testbenches at block and full-chip level.
• Experience with Verilog and PLI coding; proficiency in Verilog simulations.
• Experience in analog/mixed-signal (AMS) verification and co-simulation workflows.
• Strong debugging skills, analytical capability for complex CMOS and/or gate-level designs, and proficiency with SPICE and/or Verilog simulation tools.
• Good communication skills and ability to work effectively in a team; ability to mentor new or junior engineers.
• Scripting skills (Perl, Python) for automation and regression management.

Nice-to-have:

• Previous experience in DRAM, SRAM, or other memory-related fields.
• Experience with Real Number Models and behavioral modeling.

Education Requirements

Bachelor's or postgraduate degree in Electronics Engineering or a related engineering field is required.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.