Senior Engineer - CPU Verification (RISC-V Vector, ALU, FPU Verification)
SiFiveJob Title
Senior Engineer - CPU Verification (RISC-V Vector, ALU, FPU Verification)
Role Summary
Lead verification planning and execution for Vector, ALU, and floating-point blocks, from unit-level verification through integration into the CPU core. Work on verification strategy, testbench and test development, coverage closure, and debug to ensure correctness of execution pipelines and datapaths.
Collaborate closely with architecture, design, and verification teams to review specifications, identify risk early, and improve verification completeness. Employment contingent on background checks and legal right to work in India; export-control authorization may be required.
Experience Level
Senior-level - 4+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
Responsibilities
Own verification activities for Vector, ALU, and FPU blocks and drive verification quality across unit and core integration.
- Define and execute verification strategy, test plans, and testbench development from test planning to closure.
- Write directed and constrained-random tests, develop stimulus, assertions, checkers, and scoreboards.
- Perform coverage analysis, identify gaps, and drive coverage closure and verification sign-off.
- Design verification approaches for arithmetic, floating-point, dependency handling, forwarding, replay, flush/recovery, exceptions, and commit interactions.
- Lead root-cause debug across specification, RTL, tests, and verification infrastructure.
- Contribute reusable methodology, automation, and infrastructure to improve verification productivity across CPU programs.
Requirements
Must-have technical skills and experience; preferred items listed after.
- 4+ years of relevant experience in ASIC, CPU/core, or SoC design verification.
- Strong hands-on experience with SystemVerilog and UVM-based verification methodologies.
- Solid understanding of computer architecture and CPU microarchitecture.
- Experience verifying ALU pipelines, floating-point execution, datapath verification, issue/dispatch behavior, dependency handling, forwarding, replay, or exception handling.
- Proven experience in verification flow: test planning, stimulus generation, debug, coverage analysis, and closure.
- Good scripting or programming skills (Python, C/C++, or similar) for DV infrastructure and automation.
- Nice-to-have: experience with high-performance out-of-order CPU core verification; developing high-value assertions, checkers, and scoreboards; applying formal verification to execution logic or datapath correctness; cross-functional collaboration with architecture, design, and performance teams.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
