Senior Engineer, CMOS & Metallization Test Structure Design and Layout

Job Title

Senior Engineer, CMOS & Metallization Test Structure Design and Layout

Role Summary

Design, layout, and verify electrical test structures (scribe/non-array) to support CMOS device development, compact modeling, reliability studies, and fab process monitoring. The role partners with Process Integration, Product and Design, Electrical Characterization, Mask Development, and Design Rule teams to enable silicon validation and process integration.

Experience Level

Senior — the posting specifies a minimum of 5 years relevant experience. Expect ownership of complex test-structure projects and cross-functional collaboration.

Responsibilities

Deliver test element groups (TEGs) and related documentation to support device characterization, reliability, and manufacturing monitoring.

• Translate electrical DUT definitions into completed TEG builds with high confidence of silicon functionality.
• Design and layout memory cell–based and metallization test structures to exercise process and device parameters.
• Perform verification: DRC, LVS, schematic checks, and circuit simulation to validate designs.
• Support parametric correlation, failure analysis, and silicon debug to ensure build accuracy.
• Collaborate with Process Integration, Electrical Characterization, Mask Development, and Design Rule teams to drive process development.
• Implement novel test solutions to study failure mechanisms and monitor silicon health.
• Leverage automation and AI techniques to shorten development cycles.

Requirements

Key technical skills and on-the-job requirements. Degrees and formal education are summarized separately below.

• Proficiency with EDA tools: Cadence Virtuoso (layout and schematic) and Calibre for verification.
• Strong layout, schematic capture, and verification skills including DRC, LVS, and circuit simulation (hspice).
• Solid understanding of semiconductor device physics, parametric testing, and Design for Manufacturability (DFM).
• Knowledge of DRAM and NAND memory array architectures, fab processes, and common failure modes.
• Experience with parametric correlation, silicon debug, and verification of test structures and documentation.
• Effective problem-solving, communication, and ability to work across cultures and teams.
• Nice to have: scripting experience (Perl, Skill, UNIX shell) and familiarity with agentic SI/AI solutions.

Education Requirements

Minimum: Bachelor of Science in Electrical Engineering or Microelectronic Engineering with 5 years of relevant experience (as listed under Minimum Qualifications). Preferred: Master of Science in Electrical or Microelectronic Engineering (posting cites a Master with 3 years of experience). No certifications or explicit "equivalent experience" language was provided in the source.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.