Senior Engineer, Analog Mixed-Signal Design

Job Title

Senior Engineer, Analog Mixed-Signal Design

Role Summary

Senior analog/mixed-signal design engineer responsible for designing precision timing and mixed-signal building blocks for MEMS-based timing products used in networking, communications infrastructure, and ultra-low-power mobile devices.

Work on schematic- and post-layout design, verification, chip bring-up, and cross-functional integration with Layout, Product, Test, and Characterization teams. Compensation includes quarterly bonus and equity grants.

Experience Level

Senior level. See Education Requirements for degree-and-years guidance (degree plus minimum years of related experience determine eligibility).

Responsibilities

The role owns analog/mixed-signal circuit blocks from architecture and schematic through layout validation, verification and characterization.

• Define circuit architecture and implement analog/mixed-signal schematics to meet specifications.
• Perform calculations and verification simulations at schematic and post-layout extraction stages.
• Provide DFT/DFM provisions for designs and coordinate with layout engineers to validate critical layouts.
• Document designs and lead preliminary and final design review meetings for assigned blocks.
• Participate in chip bring-up, evaluation and characterization with emphasis on owned blocks.
• Collaborate with Product, Characterization, Test, and Applications teams to resolve issues and integrate blocks into the chip.
• Support additional projects as directed by management.

Requirements

Key technical must-haves and preferred skills for successful candidates.

Must-have:

• Detailed knowledge of CMOS circuits and noise analysis.
• Core expertise in one or more areas: Integer-N and fractional-N PLLs (Sigma-Delta and LC), Sigma-Delta ADCs (preferably >14 ENOB), temperature sensors, analog/digital filters, quartz or MEMS oscillators, sub-threshold circuits, low-noise regulators and bandgaps, or high-speed output drivers.
• Proficiency with Cadence analog design tools and common analog verification flows.
• Experience with MATLAB and Verilog-A; familiarity with OceanScript is a plus.
• Ability to oversee layout for critical blocks and perform noise analysis.

Nice-to-have:

• Published research or prototype silicon experience demonstrating successful implementations.
• Strong written and verbal communication and ability to work effectively in fast-paced teams.

Education Requirements

M.S. in Electrical Engineering or related field with a minimum of 4 years of related experience, or Ph.D. in Electrical Engineering with a minimum of 2 years of related experience. Strong academic record and published research prototyped in silicon are preferred. Fields referenced: Electrical Engineering or related technical disciplines.

About the Company

Company: SiTime

Headquarters: Sunnyvale, CA, United States

Designs and manufactures MEMS-based precision timing solutions (oscillators, clock generators, and timing ICs) for communications, computing, and consumer devices, replacing traditional quartz timing components with silicon MEMS technology.