Senior EDA Physical Design (PnR) Engineer

Job Title

Senior EDA Physical Design (PnR) Engineer

Role Summary

The Senior EDA Physical Design (PnR) Engineer develops, deploys, and supports RTL-to-GDSII physical implementation methodologies and flows for advanced semiconductor designs. This role combines hands-on physical design work, methodology development, evaluation of EDA technologies, and customer-facing technical support in a global engineering environment.

Experience Level

Senior-level. The posting requests approximately 3 to 8 years of relevant industry experience.

Responsibilities

Deliver, validate, and support production-quality physical implementation flows and provide technical support to internal teams and external customers.

• Perform physical implementation tasks: floorplanning, power planning, placement, clock tree synthesis, routing, post-route optimization, and signoff preparation.
• Diagnose and resolve timing closure, congestion, routing, power integrity, DRC/LVS, and other implementation issues.
• Develop, validate, document, and deploy reusable methodology components, scripts, checks, and automation for RTL-to-GDSII flows.
• Evaluate new EDA tool capabilities and conduct proof-of-concept comparisons to inform tool adoption and flow improvements.
• Standardize procedures and perform regression testing to ensure flow robustness, scalability, and measurable quality-of-results.
• Collaborate with EDA vendors, product engineering, and design teams to resolve issues and drive methodology adoption across sites.
• Provide hands-on customer technical support, training, demonstrations, and escalation of tool or flow issues.
• Apply software engineering practices to flow development: version control, modular design, testing, release management, and documentation.

Requirements

Key technical and professional requirements. Items marked as "nice-to-have" indicate preferred but non-mandatory skills.

• Must-have: Strong practical experience with placement, clock tree synthesis, routing, timing closure, congestion mitigation, and power/area optimization in ASIC physical design.
• Must-have: Practical knowledge of RTL-to-GDSII implementation and physical signoff methodologies; strong understanding of static timing analysis, SDC constraints, and clocking strategies.
• Must-have: Experience with industry physical-design tools (example: Synopsys Fusion Compiler, IC Compiler II, Cadence Innovus, or equivalent).
• Must-have: Proficiency in scripting and automation (Tcl, Python, or shell) in Linux/Unix environments and ability to develop maintainable flow infrastructure.
• Must-have: Strong analytical and debugging skills for diagnosing tool, flow, constraint, and design issues; ability to interpret reports and QoR metrics.
• Must-have: Effective written and verbal English communication; experience working with customers and cross-functional, distributed teams.
• Nice-to-have: Advanced scripting (Perl), experience with physically-aware synthesis and integrated Fusion Compiler flows, multi-mode/multi-corner experience, and familiarity with AI-assisted EDA techniques.
• Nice-to-have: Experience leading proof-of-concept activities and migrating or standardizing flows across multiple projects.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, Microelectronics, Semiconductor Engineering, or a related technical discipline; or equivalent practical experience.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.