Senior EDA Engineer – RTL Front-End Tools & Methodologies

Job Title

Senior EDA Engineer – RTL Front-End Tools & Methodologies

Role Summary

Senior EDA Engineer responsible for technical ownership of RTL front-end EDA methodologies, with emphasis on RTL power analysis, simulation/debug support, SDC constraint validation, automation, and vendor engagement. Works closely with design, verification, CAD, and EDA vendors to enable scalable, low-power RTL flows and integrate AI-assisted tooling where appropriate.

Hands-on role based at the Pune site with regular in-office collaboration and delivery of methodology documentation, training, and mentoring for junior engineers.

Experience Level

Senior. Target experience: 4–6 years in EDA/RTL front-end or CAD engineering roles, including 3+ years of deep hands-on RTL front-end tool and flow experience.

Responsibilities

Primary responsibilities focus on enabling and scaling RTL front-end methodologies, power analysis, simulation support, automation, and vendor collaboration.

• Own RTL front-end EDA methodologies: simulation, power analysis, and constraint validation.
• Lead RTL low-power initiatives and define power-aware RTL practices across projects.
• Enable and support RTL power analysis flows using PowerArtist and Joules: methodology definition, debug, optimization, and guidance.
• Provide expert-level RTL simulation and debug support (QuestaSim, Synopsys VCS, Cadence Xcelium).
• Validate and verify SDC constraints and ensure consistency with downstream flows.
• Drive adoption of Generative-AI capabilities and automation in EDA workflows for log analysis and productivity gains.
• Architect, develop, and maintain automation frameworks using Python (and Tcl/Shell as needed) for flow execution, regression, analysis, and reporting.
• Act as primary interface with EDA vendors: debug tool issues, raise enhancement requests, qualify versions, and align roadmaps.
• Create and maintain methodology documentation, user guidelines, and training materials.
• Mentor junior engineers and raise the technical bar of the EDA organization.

Requirements

Must-have technical skills and experience required for immediate contribution.

• 4–6 years in EDA tools, RTL front-end methodologies, or CAD engineering roles.
• 3+ years hands-on RTL power analysis experience with PowerArtist and Joules.
• Proven experience driving RTL low-power initiatives and power-optimization strategies.
• Solid understanding of SDC constraints, constraint checks, and front-end timing concepts.
• Advanced automation skills with strong proficiency in Python for flow development, analysis, and reporting.
• Experience with RTL simulation and debug using QuestaSim, Synopsys VCS, or Cadence Xcelium.
• Strong problem-solving ability to debug complex tool, power, and methodology issues.
• Ability to work on-site in Pune with a hybrid model requiring four days per week in the Pune office.

Nice-to-have:

• Experience applying Generative-AI / ML techniques to EDA workflows (log analysis, flow intelligence, automation).
• Exposure to RTL quality checks such as Lint, CDC/RDC, or power-intent verification.
• Understanding of how RTL decisions impact synthesis, STA, and physical design.
• Experience working with global, cross-functional teams and EDA vendor relationships.

Education Requirements

Not specified.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.