Senior DRAM RTL Design Engineer

Job Title

Senior DRAM RTL Design Engineer

Role Summary

Design RTL IP blocks for DRAM and memory-related subsystems from microarchitecture through RTL implementation, integration, and support for physical hardware development.

Collaborate with architecture, verification, CAD/EDA, software, and physical-design teams to drive full-chip integration, verification, and deployment of AI-assisted design and automation flows.

Experience Level

Senior — role expects approximately 3–6 years of RTL design experience as listed in the minimum qualifications.

Responsibilities

Primary responsibilities include:

• Design digital IP blocks from microarchitecture to RTL, integrate into larger systems, and support silicon bring-up.
• Define and review module interfaces and system-level architecture.
• Apply AI/ML-assisted tools and automation to accelerate RTL optimization, design-space exploration, testbench generation, corner coverage, and debug.
• Define semicustom methodology for memory design and support SoC/ASIC flows.
• Drive full-chip integration tasks including CDC, lint, synthesis, STA, and power analysis.
• Collaborate with CAD, EDA, software, architecture, verification, and physical design/layout teams.
• Oversee layout activities including floor-planning, placement, and routing.
• Perform block-level and full-chip verification: functional, timing, power, and reliability analysis.
• Provide technical mentorship and participate in design and methodology reviews.
• Contribute to methodology standardization and introduce innovations for future memory generations.

Requirements

Must-have qualifications:

• 3–6 years of RTL design experience working on digital IP or SoC designs.
• Solid knowledge of asynchronous and synchronous design concepts and CDC methodologies.
• Deep understanding of SoC design flows (lint, CDC handling, synthesis, STA, power analysis).
• Fundamentals in CMOS circuit design, device physics, and memory operation.
• Ability to work effectively with global, cross-functional teams.

Nice-to-have:

• Domain experience in DRAM (DDR5, LPDDR5, HBM) or other memory technologies; NAND design exposure is a plus.
• Experience or strong interest in AI/ML-assisted design flows, agentic AI, or advanced automation for digital design and verification.
• Experience with Spyglass and semicustom SoC/ASIC flows.
• Strong communication, problem-solving, and collaboration skills.

Education Requirements

Master's degree in Electrical Engineering or Computer Engineering (listed in Minimum Qualifications). The posting pairs this degree with ~3–6 years of RTL design experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.