Senior Digital Verification Engineer

Job Title

Senior Digital Verification Engineer

Role Summary

Lead functional verification activities for complex SoC/IP designs from specification through tapeout on a newly formed verification team. The role focuses on testbench architecture, coverage closure, debug, and automation to achieve tapeout sign-off.

Join a small, early-stage verification organization to define processes and influence product and verification flows for a highly energy-efficient processor platform.

Experience Level

Senior—10+ years of progressive ASIC/SoC design verification experience with ownership through tapeout.

Responsibilities

Primary responsibilities include building verification environments, driving coverage closure, and coordinating sign-off activities.

• Design and implement UVM/SystemVerilog testbench architecture and verification environments.
• Develop constrained-random tests, directed tests, and verification plans to meet functional goals.
• Drive functional and code coverage to tapeout sign-off on multi-million-gate SoC designs.
• Debug complex simulation failures and root-cause systemic issues.
• Develop Python-based automation for regressions, log analysis, and coverage post-processing.
• Collaborate with design, software, and program leadership to communicate verification status and risks.
• Participate in reviews, define verification closure criteria, and improve verification processes and flows.

Requirements

Must-have technical skills and practical experience; items under "Nice-to-have" increase competitiveness.

• Must-have: Expert in UVM and SystemVerilog verification methodologies and testbench architecture.
• Must-have: Proven record of driving coverage closure and tapeout sign-off on ASIC/SoC projects.
• Must-have: Strong debug skills for complex simulation failures and integration issues.
• Must-have: Proficiency in C/C++ for modeling or verification tasks.
• Must-have: Proficiency in Python for automation, regression flow development, and coverage processing.
• Must-have: Experience owning verification cycles and coordinating across teams.
• Nice-to-have: Formal verification experience (e.g., JasperGold) and post-silicon validation experience.
• Nice-to-have: Experience building or using AI/agentic flows for digital verification.
• Nice-to-have: Software/firmware co-verification experience and power-aware verification (UPF).

Education Requirements

Bachelor's, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Efficient Computer

Headquarters: Austin, TX, USA

Developer of ultra-low-power general-purpose processors using patented technology that can consume up to 100x less energy than comparable ultra-low-power processors. Their programmable platform supports standard high-level languages and AI/ML frameworks to enable long-lived, battery-powered edge devices and energy-efficient SoCs for IoT and edge AI applications.