Senior Digital / Mixed-Signal IC Design or Verification Engineer
BroadcomJob Title
Senior Digital / Mixed-Signal IC Design or Verification Engineer
Role Summary
Senior engineer within a Mixed-Signal ASIC team focused on data center enterprise storage IP. The role acts as a technical liaison across US and global design centers to drive methodology, verification quality, and automation initiatives.
Work spans digital design and mixed-signal verification activities including RTL, synthesis, timing, transistor-level design, and UVM-based verification for tape-out projects.
Experience Level
Senior-level. Typical experience: Bachelor's in Engineering + 8+ years related experience, or Master's in Engineering + 6+ years related experience.
Responsibilities
Provide technical leadership across product development lifecycle and ensure reliable integration of digital and analog blocks into mixed-signal ASICs.
- Serve as primary technical liaison between US design teams and global cross-functional teams.
- Support product development phases: testing, yield analysis, characterization, reliability, qualification, and manufacturing release.
- Conduct detailed design and verification reviews with internal and external stakeholders.
- Define system requirements, digital control functions, and block partitions for preamplifier and related products.
- Perform or oversee digital logic design, Verilog RTL coding, synthesis, static timing analysis, and place-and-route flows.
- Architect, develop, and maintain UVM-based testbenches and lead block/system-level verification to closure.
- Integrate digital cores with analog circuitry and drive transistor-level design where required.
- Lead initiatives to adopt automation and AI-assisted workflows to accelerate verification and debug.
Requirements
Must-have technical skills and experience; nice-to-have items listed separately.
- Must-have: Strong hands-on experience with ASIC EDA tools for synthesis, simulation, STA, formal verification, and place & route.
- Must-have: Proficiency in Verilog/SystemVerilog (RTL) and RTL-based design flows.
- Must-have: Deep expertise in coverage-driven verification processes and frameworks (UVM/OVM) and experience with SystemVerilog Assertions (SVA).
- Must-have: Practical scripting skills (Python, Tcl, Perl, or similar) to automate verification workflows and regression management.
- Must-have: Strong verbal and written communication skills and ability to coordinate technical problem-solving across distributed teams.
- Nice-to-have: Experience with transistor-level high-speed digital design for custom cells and blocks.
- Nice-to-have: Familiarity with silicon process technologies (CMOS, bipolar) and device physics.
- Nice-to-have: Prior work integrating AI-assisted verification or automation into testbench generation and debug.
Education Requirements
Bachelor's degree in Engineering with 8+ years of related experience, or Master's degree in Engineering with 6+ years of related experience. Degrees in related technical engineering fields are acceptable.
About the Company
Company: Broadcom
Headquarters: Irvine, California, United States
Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.
