Senior Digital/Mixed-Signal IC Design Engineer

Job Title

Senior Digital/Mixed-Signal IC Design Engineer

Role Summary

Design and verify digital controllers for high-performance analog-to-digital and digital-to-analog converters. Work spans RTL implementation, behavioral modeling, verification, and support for synthesis and place-and-route flows.

Collaborate with analog teams and customers to deliver digital backends for ADCs, PLLs and other mixed-signal blocks.

Experience Level

Senior. The posting specifies a Bachelor's (BS) plus approximately 4 years or equivalent experience in high-performance digital or mixed-signal IC development; experience expectations emphasize advanced CMOS synthesis and P&R flows.

Responsibilities

Core responsibilities include RTL development and verification for digital controllers used with high-performance data converters.

• Develop and verify Verilog/SystemVerilog RTL for digital controllers (state machines, arithmetic units, control logic).
• Create behavioral models and write testbenches to validate functionality and system-level behavior.
• Implement digital control logic for analog circuits (digital backends for ADCs, PLLs, etc.).
• Support synthesis and place-and-route flows to meet timing and area targets for nano-meter CMOS.
• Work on timing closure, static timing analysis, and multi-clock-domain constraints including clock gating.
• Support scan-chain vector generation and verification.
• Provide customer support and interface with cross-functional teams to resolve design and integration issues.

Requirements

Must-have technical skills and experience.

• Deep knowledge of Verilog RTL coding: state machines, adders, multipliers, combinational logic.
• Strong experience designing digital control for mixed-signal loops and controlling analog circuits via RTL.
• Familiarity with behavioral Verilog, including wreals, and ability to write thorough testbenches.
• Extensive experience with synthesis flows in nano-meter CMOS processes.
• Extensive experience with place-and-route flows and constraint management for mixed-signal designs.
• Practical knowledge of timing closure and static timing analysis tools.
• Experience with scan chain vector generation and verification.

Nice-to-have

• Familiarity with synthesis tools and SystemVerilog assertions.
• Experience with Cadence Encounter or similar P&R tool flows.
• Basic signal-processing knowledge (MATLAB familiarity preferred).

Education Requirements

Posting specifies a Bachelor's degree (BS) plus ~4 years of relevant experience, or equivalent practical experience. No specific field-of-study is stated; degree in a technical discipline (e.g., electrical/computer engineering or related) is implied but not required by text.

About the Company

Company: Omni Design Technologies

Headquarters: Hyderabad, India

Omni Design Technologies specializes in the development of advanced solutions for electronic design automation, focusing on ASIC and FPGA verification processes. The company provides high-quality verification tools and resources for engineers in the semiconductor industry, ensuring efficient design and reliable performance.