Senior Digital Engineer

Job Title

Senior Digital Engineer

Role Summary

Design, architect and integrate low-power digital circuits for mixed-signal data conversion and power-management products. Support the full silicon product lifecycle from concept through mass production and collaborate closely with Analog, Verification, and P&R teams to deliver reliable, optimized silicon.

Experience Level

Senior — typically requires more than 5 years of digital design experience in areas such as wireless handheld, data conversion, or power management.

Responsibilities

The role focuses on RTL design, integration, verification support, and delivery of production-ready silicon.

• Translate high-level requirements into digital micro-architecture and RTL (Verilog/SystemVerilog).
• Design RTL to meet timing, area, power and standards requirements; generate timing constraints and synthesis-ready RTL.
• Integrate blocks at top level, run block and top-level simulations, and support RTL and gate-level simulation debug.
• Participate in design flow activities: lint, CDC/RDC checks, synthesis, timing analysis, and interaction with P&R for timing closure.
• Support DFT strategy and implementation and review test-case development.
• Collaborate with analog and verification teams to develop complex pre-silicon test scenarios and behavioral models.
• Perform silicon evaluation, document device errata, propose work-arounds and implement engineering changes as needed.
• Prepare block- and chip-level design documentation and participate in design reviews and project checklists.

Requirements

Must-have technical skills and attributes.

• Fluent in Verilog / SystemVerilog for digital CMOS RTL design.
• Strong understanding of ASIC design methodology, lint tools, CDC and RDC tools.
• Proven ability to debug RTL and gate-level simulations and strong block- and chip-level verification knowledge.
• Experience interacting with P&R teams and familiarity with STA and timing closure practices.
• Mandatory competence in written and verbal English and ability to work independently and collaboratively.
• Willingness to travel domestically or internationally on short notice.

Nice-to-have.

• Experience with mixed-signal design methodologies and AMS/SystemVerilog behavioral modeling.
• Experience developing design constraints and hand-off to P&R; STA, low-power design techniques including UPF, power analysis and optimization.
• Experience with advanced verification methodologies (UVM) and industry-standard protocols such as AMBA or I2C.

Education Requirements

Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline is required (as stated in the posting).

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.