Senior Digital Design Engineer, Air Dominance and Strike

Job Title

Senior Digital Design Engineer, Air Dominance and Strike

Role Summary

Senior FPGA/digital design engineer on the Air Dominance and Strike electrical engineering team. Responsible for designing, implementing, and integrating RTL for FPGA and SoC platforms used in high-performance avionics and mission-critical embedded systems.

The role covers the full development cycle from requirements and microarchitecture through RTL implementation, simulation, timing closure, lab bring-up, and system integration in support of autonomous air platforms.

Experience Level

Senior — typically 8+ years of FPGA, ASIC, or closely related digital design experience (the posting requests 8+ years; preferred candidates may have 12+ years).

Responsibilities

You will own design and delivery of FPGA/SoC-based digital subsystems and collaborate across hardware, software, and systems teams.

• Design and implement RTL in VHDL, Verilog, or SystemVerilog for FPGA and SoC systems.
• Translate system requirements into microarchitecture and interface definitions.
• Own major functional blocks or full FPGA designs from architecture through integration and timing closure.
• Develop and execute simulation, synthesis, and implementation flows; achieve timing and resource closure.
• Debug functional, timing, and integration issues in simulation and on hardware.
• Support board bring-up, lab validation, and system integration on target platforms.
• Collaborate with hardware, embedded software, systems, and verification engineers to deliver end-to-end solutions.
• Participate in design and code reviews and maintain technical documentation.
• Contribute to reusable IP, coding standards, and development workflows; support rapid prototyping consistent with production rigor.

Requirements

Must-have technical skills and experience.

• 8+ years of FPGA, ASIC, or closely related digital design experience.
• Proficiency in VHDL and/or Verilog/SystemVerilog.
• Hands-on experience with simulation, synthesis, implementation, and timing closure on modern FPGA platforms.
• Practical debug experience in simulation and on hardware (board bring-up, lab validation).
• Strong digital design fundamentals: clocking, resets, state machines, CDC awareness, and interface design.
• Experience with Linux-based development environments, Git-based workflows, and scripting in Tcl and/or Python.
• Strong written and verbal communication skills.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

Requirements

Nice-to-have / preferred qualifications.

• 12+ years of FPGA development experience.
• Experience owning a major functional block, subsystem, or full FPGA design from concept through integration.
• Familiarity with AMD (Xilinx), Intel/Altera, or Lattice FPGA toolchains and AMD (Xilinx) Vitis or similar tooling.
• Experience with embedded systems and hardware/software co-design.
• Familiarity with high-speed/embedded interfaces: Ethernet, PCIe, JESD204, SPI, I2C, UART, CAN, or MIL-STD-1553.
• Familiarity with DO-254 or other military/safety-critical development standards.
• Experience building reusable IP, verification infrastructure, CI/CD flows, or reproducible build environments.
• Familiarity with Jira and automated regression or reproducible build tooling.

About the Company

Company: Anduril

Headquarters: Costa Mesa, CA, USA

Anduril is a defense technology company that builds autonomous systems, AI, sensor-fusion, and computer-vision-enabled platforms for U.S. and allied military and intelligence customers, powered by its Lattice OS to accelerate delivery of operational capabilities.