Senior Digital Design Engineer
Allegro MicroSystemsJob Title
Senior Digital Design Engineer
Role Summary
Lead and execute digital architecture and design for mixed-signal motor-drive ICs and related IP, delivering tapeout-ready RTL and ensuring first-pass silicon success.
Work with the Edinburgh team and coordinate across Systems, Analog, and Marketing to define technical direction, mentor engineers, and manage delivery across RTL, verification, DFT, and synthesis flows.
Experience Level
Senior — requires significant hands-on experience; the source specifies 8+ years in digital design or architecture.
Responsibilities
Primary responsibilities for the role include technical leadership, project delivery, and cross-functional coordination.
- Take ownership of digital design project schedules and delivery for the Edinburgh team (RTL through tapeout).
- Define and drive the digital architectural roadmap for motor-driver products, from IP to full SoC.
- Coordinate RTL, verification, DFT, and synthesis activities to meet tapeout milestones.
- Identify technical bottlenecks and resource gaps; manage technical risk and mitigation plans.
- Act as the primary digital technical contact for the Edinburgh centre with Marketing, Systems, and Analog teams.
- Partner with verification to define success criteria, ensure functional coverage, and oversee Functional Safety considerations.
- Mentor and guide engineers on technical approach, reviews, and delivery practices.
- Travel domestically and internationally up to 10–20% to support customers, vendors, and off-site teams.
Requirements
Must-have qualifications, followed by concise nice-to-have items.
Must-have:
- 8+ years of experience in digital design or architecture covering algorithmic IP to full SoC designs.
- Deep understanding of digital design workflow and front-end flows (RTL, verification, DFT, synthesis).
- Experience with CPU subsystems and interconnect fabrics such as AMBA/AXI.
- Proven track record of leading projects, coordinating cross-functional teams, and delivering to schedule.
- Strong verbal and written communication skills for technical presentations and roadmaps.
- Experience defining verification success criteria and working closely with verification teams.
- Willingness to travel up to 10–20%.
Nice-to-have:
- Experience with Cadence front-end toolsets for RTL/verification flows.
- Direct experience delivering ISO 26262 compliant designs (ASIL B/D).
Education Requirements
PhD or Master’s degree in Electronics or a related technical field (explicitly stated in the source).
About the Company
Company: Allegro MicroSystems
Headquarters: Manchester, New Hampshire, USA
Global semiconductor company with over 30 years of innovation, developing semiconductor devices and design enablement tools. Allegro focuses on device development, foundry partnerships, IP characterization, and design automation to support product roadmaps and technology advancement.
