Senior DFX Power Methodology Engineer

Job Title

Senior DFX Power Methodology Engineer

Role Summary

Senior engineer responsible for developing DFX power, thermal and voltage-noise methodologies for post-silicon validation and manufacturing test of high-performance GPUs. Work on low-power and thermal solutions, post-silicon data analysis, and deployment of DFT methodologies using applied machine learning and generative AI.

The role is cross-functional and partners with product development, power architecture, RTL and physical design teams to improve chip quality and manufacturability.

Experience Level

Senior. Hiring guidance in the posting indicates: BSEE (or equivalent experience) with 12+ years, MSEE with 10+ years, or PhD with 6+ years of relevant DFT and power experience.

Responsibilities

Primary responsibilities include designing methodologies, analyzing data, and enabling manufacturing tests under demanding power and thermal conditions.

• Develop and innovate DFX power, thermal and voltage-noise methodologies for manufacturing tests.
• Design low-power and thermal solutions for datacenter GPU test conditions.
• Collaborate with product development and power architecture teams to implement new methodologies addressing outgoing quality.
• Perform post-silicon power and thermal data analysis to inform next-generation solutions.
• Develop and deploy DFT/DFX methodologies leveraging applied ML and generative AI.
• Mentor and guide junior engineers on test design, trade-offs, cost, and quality.
• Support silicon debug and bring-up on ATE and SLT platforms.

Requirements

Must-have technical skills and preferred additions are listed below.

• Proven experience in DFT design and power methodology at senior level.
• Strong understanding of VLSI power, timing and voltage-noise concepts and their interaction with DFT.
• Experience with post-silicon debug and bring-up on ATE or SLT platforms.
• Proficiency with statistical tools for data analysis and extracting actionable insights.
• Practical exposure to RTL and clock design, static timing analysis (STA), place-and-route flows.
• Ability to prototype solutions programmatically and translate algorithms into production test harnesses.
• Excellent written and verbal communication and the ability to work across functions.
• Nice-to-have: experience with power analysis, thermal analysis and IR-drop tools; experience applying AI/ML to EDA problems; prior responsibility managing DFT power methodology; post-silicon thermal and IR-drop debug experience.

Education Requirements

Degree or equivalent experience expected: BSEE (or equivalent experience) with ~12+ years, MSEE with ~10+ years, or PhD with ~6+ years in DFT design, power engineering, VLSI or related technical fields. The posting explicitly allows equivalent practical experience in lieu of a listed degree.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.