Senior DFT Methodology Engineer

Job Title

Senior DFT Methodology Engineer

Role Summary

Design and deploy design-for-test (DFT) methodologies and architectures to ensure next-generation SoC designs are testable, debuggable, and secure from first bring-up. Work on DFT architecture, RTL-level methodology, verification, pattern generation, and post-silicon validation for complex semiconductor chips.

Collaborate with timing, physical design, software, bring-up, and production teams and mentor junior engineers to drive methodology adoption across product generations.

Experience Level

Senior - 10+ years of hands-on experience in SoC architecture, RTL design, and verification.

Responsibilities

Primary responsibilities include creating and deploying DFT methodologies and working across functions to balance cost, quality, and time-to-product.

• Architect and implement test access mechanisms and DFT features such as IEEE 1149.1, IEEE 1500, IEEE 1687, 1838, memory BIST, memory dump, and DFX/security-related methodologies.
• Develop and verify RTL DFT components, generate test patterns, and validate test logic on complex multi-million-gate designs using vendor tools.
• Partner with timing, physical design (STA, place-and-route, power), software, bring-up, and production teams to make design trade-offs.
• Support silicon debug and ATE bring-up, including understanding pattern formats, failure processing, and test program development.
• Mentor and guide junior engineers on test design choices, methodology adoption, and trade-offs between cost and quality.

Requirements

Key technical and interpersonal requirements. Items marked "Must-have" are required; "Nice-to-have" indicate preferred skills.

• Must-have: 10+ years of hands-on experience in SoC architecture, RTL design, and verification on large-scale semiconductor designs.
• Must-have: Experience using vendor tools to verify and validate test patterns and test logic on complex designs.
• Must-have: Practical exposure to RTL & clock design, STA, place-and-route, and power to evaluate design trade-offs.
• Must-have: Experience with silicon debug and ATE bring-up, including pattern formats and failure analysis.
• Must-have: Strong written and verbal communication and collaboration skills.
• Nice-to-have: Programming/scripting skills (Perl, Python, Tcl) and demonstrated history of deploying advanced DFT methodologies across product generations.
• Nice-to-have: Experience or knowledge of DFT security and hardware/system security.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field - or equivalent practical experience in the DFT/SoC domain.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.