Skip to main content
NVIDIA logo

Senior DFT Methodology Engineer

NVIDIA
October 5, 2026
Full-time
Remote friendly (Santa Clara, California, United States)
Worldwide
$168,000 - $310,500 USD yearly
DFT Jobs, Level - Senior

Job Title

Senior DFT Methodology Engineer

Role Summary

The Senior DFT Methodology Engineer will architect and develop design-for-test methodologies to ensure NVIDIA's next-generation SoCs are testable, debuggable, and secure from first bring-up through production. The role works within the DFT/Design-for-Test team and partners with RTL, timing, physical design, software, bring-up, and production teams to balance cost, quality, and manufacturability.

Experience Level

Senior - typically 10+ years of relevant industry experience in SoC architecture, RTL design, verification, and DFT.

Responsibilities

Lead design and deployment of DFT methodologies across multiple product generations and collaborate with cross-functional teams to integrate testability into complex SoCs.

  • Design and implement test access mechanisms and DFT architectures (standards referenced in role: 1149.1, 1500, 1687, 1838), memory BIST, memory dump, and DFX security methodology.
  • Architect, develop, and deploy DFT flows including RTL design, verification, and pattern generation for production chips.
  • Collaborate with timing, physical design, software, bring-up, and production teams to make cost/quality trade-offs.
  • Validate and verify test patterns and logic on large, multi-million-gate designs using vendor tools and methodologies.
  • Mentor and guide junior engineers on test design decisions and methodology adoption.

Requirements

Core technical and practical requirements for immediate contribution.

  • 10+ years of hands-on experience in SoC architecture, RTL design, and verification.
  • Proven, documented experience in DFT architecture and methodology for complex semiconductor designs.
  • Experience using vendor tools to verify and validate test patterns and test logic on large designs.
  • Familiarity with RTL & clock design, static timing analysis (STA), place-and-route, and power trade-offs.
  • Experience with silicon debug and bring-up on ATE, including pattern formats, failure processing, and test program development.
  • Strong analytical, written, and oral communication skills; ability to work across functions and influence design decisions.
  • Nice-to-have: DFT security/hardware system security knowledge; scripting skills (Perl, Python, Tcl); record of deploying advanced DFT methodologies; experience mentoring and driving methodology adoption.

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering (or equivalent practical experience). The posting allows equivalent experience in related technical domains in lieu of the listed degrees.


About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.

NVIDIA logo

Date Posted: 2026-10-03