Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Define, architect, and execute Design-for-Test strategies for high-performance SoCs/ASICs. Work with front-end design, physical design, verification, and product/test engineering teams to ensure high test coverage, silicon quality, and efficient production test enablement.

Experience Level

Senior — typically 3+ years of hands-on DFT experience in advanced SoC/ASIC development.

Responsibilities

Responsible for pre-silicon DFT architecture and post-silicon bring-up to enable production testing and yield improvement.

• Architect and implement Scan, ATPG, MBIST, and JTAG/IEEE (1149.1, 1500, 1687/IJTAG) DFT solutions.
• Perform scan chain insertion, stitching, and timing/power optimization.
• Integrate MBIST controllers, repair mechanisms, and custom memory test routines.
• Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware) and perform fault grading.
• Execute gate-level Verilog/SystemVerilog SDF simulations for DFT validation and vector cleanliness.
• Run DFT linting and rule checks using industry tools (e.g., SpyGlass DFT, Tessent, Modus, TetraMAX).
• Convert ATPG/MBIST patterns to tester formats (WGL, STIL) and support ATE deployment.
• Lead post-silicon bring-up: debug DFT features, analyze failures, and optimize test time to improve yield.
• Collaborate with Product and Test Engineering for production diagnostics and test strategy alignment.

Requirements

Must-have technical skills and experience.

• 3+ years hands-on DFT experience on advanced SoC/ASIC projects.
• Proficiency in Verilog/SystemVerilog for DFT integration and simulation.
• Practical experience with scan insertion, compressed scan architectures, and boundary scan.
• ATPG expertise: generating, debugging, and fault-grading Stuck-at and At-Speed patterns.
• MBIST experience: insertion, architecture, and memory repair schemes.
• Solid knowledge of JTAG (IEEE 1149.1) and TAP controller integration.
• Experience with post-silicon pattern bring-up and supporting production yield ramps.
• Familiarity with DFT tools and flows (linting, ATPG, pattern conversion).

Nice-to-have:

• Scripting for flow automation (Tcl, Python, Perl).
• Advanced DFT topics: high-speed IO/SerDes testing and analog DFT concepts.
• Familiarity with synthesis (Synopsys Design Compiler, Cadence Genus) and STA constraints for DFT modes.

Education Requirements

Not specified.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.