Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

K2 Space seeks a Senior Design-for-Test (DFT) Engineer to lead DFT architecture and implementation for complex mixed-signal SoCs. The role partners with RTL, verification, and physical-design teams to ensure high test coverage, manufacturability, and successful first-pass silicon.

Experience Level

Senior — requires 7+ years of experience in DFT for complex SoCs.

Responsibilities

Primary responsibilities focus on DFT architecture, RTL-level insertion, ATPG flow ownership, and silicon debug for mixed-signal SoCs.

• Define and implement DFT architecture for mixed-signal SoCs (scan, MBIST/LBIST, boundary scan).
• Lead RTL-level DFT insertion: scan chain insertion and optimization, test point insertion, and low-power DFT methods.
• Own ATPG flow: generate stuck-at, transition, and path delay patterns; drive coverage closure, pattern optimization, and failure debug.
• Develop mixed-signal DFT strategies, including wrapper-based test and analog test/BIST approaches.
• Collaborate with RTL, verification, and physical-design teams to align timing, constraints, and scan integration (reordering, compression).
• Drive DFT verification and signoff: coverage metrics, DFT rule checks, gate-level simulation, and pattern validation.
• Support silicon bring-up and debug: analyze tester failures, yield issues, and ATPG-to-silicon correlation.
• Contribute to methodology development, automation, and flow improvements.

Requirements

Must-have:

• 7+ years of hands-on DFT experience for complex SoCs.
• Practical experience with RTL DFT insertion (scan, compression, test points) and ATPG tools/flows.
• Deep knowledge of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), and coverage-closure strategies.
• Experience with low-power DFT techniques and mixed-signal test methodologies.
• Strong debugging skills across RTL, gate-level, and silicon.

Nice-to-have:

• MBIST/LBIST implementation and memory repair flow experience.
• Familiarity with IEEE 1149.x (JTAG/boundary scan) and multi-voltage/power-aware DFT.
• Exposure to physical-design impacts on DFT (scan reordering, congestion, timing) and scripting for automation.
• Experience with high-speed interfaces (SerDes), RF/mixed-signal SoCs, A0 bring-up, or working in distributed cross-functional teams.

Education Requirements

B.S. or M.S. in Electrical Engineering or a related technical field (e.g., Electrical/Computer Engineering, Computer Science, Physics).

About the Company

Company: K2 Space

Headquarters: United States

K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.