Senior DfT Engineer

Job Title

Senior DfT Engineer

Role Summary

Join NXP's design team in Chandler, AZ as a Design-for-Test (DfT) engineer focused on inserting, verifying, and debugging test structures for mixed-signal and digital chips. The role works closely with product, design, test, validation, and quality teams to deliver testable silicon.

Experience Level

Senior — the team is seeking candidates with approximately 3–8 years of relevant experience in DfT, digital design, or related roles.

Responsibilities

Key responsibilities include designing and validating DfT features, supporting silicon bring-up, and producing design documentation.

• Collaborate with product definers, analog/digital design leads, test, validation and quality engineers to define testability requirements.
• Design and insert DfT for complex analog/mixed-signal IP, standard macros (RAM, ROM, NVM, ADC, DAC) and digital logic.
• Develop high-quality RTL using Verilog and SystemVerilog.
• Define verification plans, write and debug tests in the chip-level DV environment.
• Perform scan insertion, chain optimization and length balancing, P&R-aware rerouting of chains, and test-point insertion.
• Generate ATPG patterns, run simulations, and debug test failures.
• Support test engineers during silicon debug and on customer returns.
• Participate in design and test reviews and produce/maintain DfT architecture and design documentation.
• Troubleshoot DfT issues throughout the development lifecycle and stay current with industry tools and methodologies.

Requirements

The list below summarizes required and preferred skills for the role.

• Must-have:
  • Minimum 3 years of experience in DfT, digital design, or digital architecture (seeking ~3–8 years).
  • Strong RTL coding skills in Verilog and SystemVerilog.
  • Practical experience with scan insertion, ATPG pattern generation, chain optimization, and test-point insertion.
  • Experience debugging test patterns and supporting silicon bring-up.
  • Willingness to relocate to the Phoenix metro area and be in NXP's Chandler office a minimum of 3 full days per week.
  • Good problem solving, communication, teamwork, planning, and attention to detail.
• Nice-to-have:
  • Experience with DfT for analog/mixed-signal IP and complex macros (RAM/ROM/NVM/ADC/DAC).
  • Knowledge of P&R-aware rerouting and length balancing techniques.

Education Requirements

Master's degree (MSEE) with coursework relevant to Digital Design, RTL coding, DfT, Computer Architecture, or Digital Verification is stated as the expected qualification.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.