Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

As a Senior DFT Engineer at QFocus Technologies, you will define, architect, and execute Design-for-Test strategies for advanced SoCs/ASICs. You will work with front-end design, physical design, verification, and product/test engineering to ensure high test coverage, silicon quality, and manufacturable test flows.

Experience Level

Senior — 3+ years of hands-on DFT experience in advanced SoC/ASIC development.

Responsibilities

Primary responsibilities cover pre-silicon DFT implementation and post-silicon production support.

• Define and implement DFT architectures: Scan, ATPG, MBIST, and JTAG/IEEE (1149.1, 1500, 1687/IJTAG).
• Perform scan chain insertion, stitching, and optimization for timing closure and power compatibility.
• Integrate MBIST controllers, repair mechanisms, and custom memory test routines.
• Generate ATPG patterns (Stuck-at, At-Speed, Cell-Aware) and validate via gate-level (SDF) simulations.
• Run DFT linting and rule checks using industry tools (e.g., SpyGlass DFT, Tessent, Modus, TetraMAX).
• Translate pre-silicon patterns to tester formats (WGL, STIL) and support ATE deployment.
• Support post-silicon bring-up: debug DFT features, convert patterns, analyze failures, and collaborate with PTE to improve yield and test time.

Requirements

Must-have skills and experience for immediate contribution.

• 3+ years hands-on DFT experience in advanced SoC/ASIC projects.
• Proficiency in Verilog/SystemVerilog for DFT integration, wrapper creation, and simulation debugging.
• Experience with scan insertion, compressed scan architectures (EDT/SmartTest), and boundary scan integration.
• ATPG expertise: pattern generation, debugging, and fault-grading for Stuck-at and At-Speed tests.
• MBIST experience: insertion, architecture, and memory repair schemes.
• Familiarity with JTAG/IEEE 1149.x standards, TAP controllers, and board/chip-level test logic.
• Experience with post-silicon pattern bring-up and production yield support.

Nice-to-have:

• Scripting for automation (Tcl, Python, Perl).
• Knowledge of advanced DFT concepts (High-Speed IO testing, SerDes loopback, Analog DFT).
• Familiarity with synthesis and STA tools (Synopsys Design Compiler, Cadence Genus) and DFT-related constraints.

Education Requirements

Not specified.

About the Company

Company: QFocus Technologies

Engineering services firm focused on semiconductor and SoC/ASIC design, verification, and test. Provides technical staffing and engineering solutions for hardware development teams, including DFT, verification, and post-silicon bring-up support.