Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Implement and verify design-for-test (DFT) solutions for complex hierarchical SoC and ASIC designs to achieve first-pass silicon success. Work within the SoC/ASIC DFT development team and coordinate with physical design and ATE test teams to deliver test strategies aligned with industry practices.

Experience Level

Senior level. Minimum 3 years of DFT design and verification experience required; 5+ years preferred for senior candidates.

Responsibilities

Primary responsibilities include DFT architecture, insertion, verification, and production test support.

• Design and implement DFT architectures for block-level and top-level integration in hierarchical SoC/ASIC designs.
• Perform scan insertion, test point insertion, and implement test compression (SSN or equivalent).
• Validate Serial Stream Network (SSN) topology, manage scan chain balancing and clock domain crossings.
• Integrate boundary-scan (IEEE 1149.x) and other chip-level test access mechanisms.
• Generate and analyze ATPG patterns for stuck-at, transition, and path delay faults to ensure test coverage.
• Execute DFT verification including Verilog and gate-level simulations.
• Collaborate with physical design and cross-functional teams to resolve DFT/testing timing issues.
• Work with ATE engineers to prepare and validate timing and pattern files (STIL/WGL) for tester compatibility.
• Support silicon bring-up, production test debugging, diagnostics, and failure analysis.

Requirements

Must-have technical skills and experience required for the role; additional skills are beneficial.

• Minimum 3 years of hands-on DFT design and verification experience (5+ years preferred).
• Strong knowledge of scan-based test architectures, test compression, and hierarchical DFT implementation.
• Hands-on experience with DFT tools such as Siemens Tessent.
• Proficiency in ATPG generation, fault coverage analysis, and gate-level DFT verification.
• Familiarity with ATE test flows and pattern validation on platforms such as Advantest or Teradyne.
• Strong scripting skills (TCL, Perl, or Python) for DFT automation.
• Nice-to-have: experience with SSN compression architectures, STIL/WGL pattern handling, and production failure analysis.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field. Equivalent practical experience is acceptable.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.