Senior DFT Engineer

Job Title

Senior DFT Engineer

Role Summary

Lead DFT strategy and execution for digital ASIC designs, working with RTL and physical design teams to ensure testability, generate and validate test patterns, and deliver production test programs.

Drive DFT implementation, debug test failures, and optimize test flows to meet performance and schedule targets.

Experience Level

Senior — minimum of 5 years of hands-on DFT experience in a product company.

Responsibilities

The role focuses on defining DFT methodology, producing test assets, validating implementations, and collaborating across RTL and physical design teams.

• Define DFT strategy, methodologies, and test plans.
• Specify and implement test and debug structures (scan, MBIST/LBIST, IEEE 1500, JTAG).
• Create test vectors and simulate/validate in multiple modes; generate production test programs for device screening.
• Collaborate with physical design to close testability and timing requirements; verify post-PD designs meet DFT needs.
• Analyze and debug test failures; perform logic diagnosis and yield learning.
• Run and optimize test compression and at-speed/stuck‑at flows.
• Trade off test options versus product performance and schedule; drive execution to resolve DFT flow issues.

Requirements

Core technical skills and tool experience required to perform independently in a product environment.

Must-have:

• Hands-on experience with commercial test generation tools for large complex designs.
• Strong knowledge of DFT techniques: JTAG, ATPG, scan, test compression, MBIST/LBIST, IEEE 1500, logic diagnosis.
• Experience generating test patterns and debugging test failures.
• Experience with RTL simulation, synthesis, and backend implementation flows.
• Experience with stuck-at and at-speed testing techniques and running test compression flows.
• Practical experience with Cadence Genus and Modus; good understanding of Verilog/VHDL.
• Proficient in TCL and Python scripting for automation.

Nice-to-have:

• Exposure to low-power design techniques.
• Experience with test program release processes and production device screening.

Education Requirements

B.E./B.Tech./M.E./M.Tech in VLSI or a closely related field listed. The posting also specifies a minimum of 5 years of working experience in DFT flow at a product company (or equivalent practical experience).

About the Company

Company: Omni Design Technologies

Headquarters: Hyderabad, India

Omni Design Technologies specializes in the development of advanced solutions for electronic design automation, focusing on ASIC and FPGA verification processes. The company provides high-quality verification tools and resources for engineers in the semiconductor industry, ensuring efficient design and reliable performance.